ISO807 Datasheet, PDF (10/12 Pages) Burr-Brown (TI) – Isolated 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER

CAP
CAP (pin 15) is the output of the internal reference buffer.
A 2.2µF tantalum capacitor should be placed as close as
possible to the CAP pin from ground to provide optimum
switching currents for the CDAC throughout the conversion
cycle. This capacitor also provides compensation for the
output of the buffer. Using a capacitor any smaller than 1µF
can cause the output buffer to oscillate and may not have
sufficient charge for the CDAC. Capacitor values larger than
2.2µF will have little affect on improving performance. See
Figure 6.
The output of the buffer is capable of driving up to 1mA of
current to a DC load. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degra-
dation of the converter.
LAYOUT
POWER
For optimum performance, tie the analog and digital power
pins to the same +5V power supply and tie the analog and
digital grounds together. As noted in the electrical specifica-
tions, the ISO807 uses 50% of its isolated power for the
analog circuitry. The ISO807 front end should be considered
as an analog component.
The +5V power for the A/D should be separate from the +5V
used for the system’s digital logic. Connecting V_DIG1 (pin
10) directly to a digital supply can reduce converter perfor-
mance due to switching noise from the digital logic. For best
performance, the +5V supply can be produced from what-
ever analog supply is used for the rest of the analog signal
conditioning. If +12V or +15V supplies are present, a simple
+5V regulator can be used. Although it is not suggested, if
the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered
digital supply or a regulated analog supply, both V_DIG1 and
V_ANA should be tied to the same +5V source.
GROUNDING
Two ground pins are present on the ISO807 input side.
DGND1 is the digital supply ground. AGND is the analog
supply ground. AGND is the ground to which all analog
signals internal to the A/D are referenced. AGND is more
susceptible to current induced voltage drops and must have
the path of least resistance back to the power supply.
The ground pin of the A/D should be tied to an analog
ground plane, separated from the system’s digital logic
ground, to achieve optimum performance. Both analog and
digital ground planes should be tied to the “system” ground
as near to the power supplies as possible. This helps to
prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.
INPUT RANGE
OFFSET ADJUST
RANGE (mV)
GAIN ADJUST
RANGE (mV)
±10V
±15
±60
0 to 5V
±4
±30
0 to 4V
±3
±30
TABLE VI. Offset and Gain Adjust Ranges for Hardware
Calibration (see Figure 3a).
INPUT
RANGE
(V)
±10
W/ RESISTORS
RANGE (mV)
–10 ≤ BPZ ≤ 10
0 to 5
–3 ≤ UPO ≤ 3
0 to 4
–3 ≤ UPO ≤ 3
Note: (1) High Grade.
OFFSET ERROR
W/OUT RESISTORS
RANGE (mV)
TYP (mV)
0 ≤ BPZ ≤ 35
+15
–12 ≤ UPO ≤ –3
–7.5
–10.5 ≤ UPO ≤ –1.5
–6
W/ RESISTORS
RANGE (% FS)
–0.4 ≤ G ≤ 0.4
0.15 ≤ G⁽¹⁾ ≤ 0.15
–0.4 ≤ G ≤ 0.4
0.15 ≤ G⁽¹⁾ ≤ 0.15
–0.4 ≤ G ≤ 0.4
–0.15 ≤ G⁽¹⁾ ≤ 0.15
GAIN ERROR
W/OUT RESISTORS
RANGE (% FS)
TYP
–0.3 ≤ G ≤ 0.5
–0.1 ≤ G⁽¹⁾ ≤ 0.2
–1.0 ≤ G ≤ 0.1
–0.55 ≤ G⁽¹⁾ ≤ –0.05
–1.0 ≤ G ≤ 0.1
–0.55 ≤ G⁽¹⁾ ≤ –0.05
+0.05
+0.05
–0.2
–0.2
–0.2
–0.2
TABLE VII. Range of Offset and Gain Errors with and without External Resistors
®
ISO807
10