DAC7614 Datasheet, PDF (10/12 Pages) Burr-Brown (TI) – Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER

REFERENCE INPUTS
The reference inputs, V_REFL and V_REFH, can be any voltage
between V_SS + 2.25V and V_DD – 2.25V provided that
V_REFH is at least 1.25V greater than V_REFL. The minimum
output of each DAC is equal to V_REFL – 1LSB plus a small
offset voltage (essentially, the offset of the output op amp).
The maximum output is equal to V_REFH plus a similar
offset voltage. Note that V_SS (the negative power supply)
must either be connected to ground or must be in the range
of –4.75V to –5.25V. The voltage on V_SS sets several bias
points within the converter. If V_SS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.6 milliamp. Bypassing the reference volt-
age or voltages with a 0.1µF capacitor placed as close as
possible to the DAC7614 package is strongly recommended.
DIGITAL INTERFACE
Figure 3 and Table I provide the basic timing for the
DAC7614. The interface consists of a serial clock (CLK),
serial data (SDI), and a load DAC signal (LOADDACS). In
addition, a chip select (CS) input is available to enable serial
communication when there are multiple serial devices. An
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
t_DS
Data Valid to CLK Rising
25
ns
t_DH
Data Held Valid after CLK Rises 20
ns
t_CH
CLK HIGH
30
ns
t_CL
CLK LOW
50
ns
t_CSS
CS LOW to CLK Rising
55
ns
t_CSH
CLK HIGH to CS Rising
15
ns
t_LD1
LOADDACS HIGH to CLK Rising 40
ns
t_LD2
CLK Rising to LOADDACS LOW 15
ns
t_LDDW
LOADDACS LOW Time
45
ns
t_RSSH
RESETSEL Valid to RESET LOW 25
ns
t_RSTW
RESET LOW Time
70
ns
t_S
Settling Time
10
µs
TABLE I. Timing Specifications (T_A = –40°C to +85°C).
asynchronous reset input (RESET) is provided to simplify
start-up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 3. The first two bits select the
DAC register that will be updated when LOADDACS goes
LOW (see Table II). The next two bits are not used. The last
12 bits is the DAC code which is provided, most significant
bit first.
SDI
CLK
CS
LOADDAC
SDI
CLK
LOADDAC
V_OUT
RESET
RESETSEL
A1 A0 X
(MSB)
X D11 D10 D9
(LSB)
D3 D2 D1 D0
tcss
t_LD1
t_DS
t_CL
t_DH
t_CH
t_CSH
t_LD2
t_LDDW
t_LDDW
t_S
1 LSB
ERROR BAND
t_RSSH
t_S
t_RSTW
1 LSB
ERROR BAND
FIGURE 3. DAC7614 Timing.
®
DAC7614
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