ADS902 Datasheet, PDF (10/11 Pages) Burr-Brown (TI) – 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER

When selecting this reference circuit, the trade-offs are
variations in the reference voltages due to component toler-
ances and power supply variations. In either case, it is
recommended to bypass the reference ladder with at least
0.1µF ceramic capacitors as shown in Figure 6. The purpose
of the capacitors is twofold; they will bypass most of the
high frequency transient noise which results from feedthrough
of the clock and switching noise from the S/H stages and
secondly, they serve as a charge reservoir to supply instan-
taneous current to internal nodes.
consideration must be made to provide a clock with very low
jitter. Clock jitter leads to aperture jitter (t_A) which can be the
ultimate limitation to achieving good SNR performance.
Equation (5) shows the relationship between aperture jitter,
input frequency and the signal-to-noise ratio:
SNR = 20log₁₀ [1/(2 π f_IN t_A)]
(5)
For example, with a 5MHz full-scale input signal and an
aperture jitter of t_A = 20ps rms, the SNR is clock jitter
limited to 54dB.
PRECISE REFERENCE SOLUTION
For those applications requiring a higher level of dc accu-
racy and drift, a reference circuit with a precision reference
element might be used (see Figure 7). A stable +2.5V
reference voltage is established by a two terminal bandgap
reference diode, the REF1004-2.5. Using a general-purpose
single-supply dual operational amplifier (A1), like an
OPA2237, OPA2234 or MC34072, the two required refer-
ence voltages for the ADS902 can be generated by setting
each op amp to the appropriate gain. For example, set REFT
to +3.25V and REFB to +2.25V.
+V_S
10kΩ
5kΩ
REF1004
+2.5V
+V_S
1/2 A₁
R_F1
R_G1
10Ω
Top
Reference
(Pin 22)
DIGITAL OUTPUTS
The digital outputs of the ADS902 are standard CMOS
stages and designed to be compatible with both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: V_OL = 0.4V, V_OH = 2.4V, which allows
the ADS902 to directly interface to 3V-logic. The digital
outputs of the ADS902 uses a dedicated digital supply pin
(see Figure 8). By adjusting the voltage on LV_DD, the digital
output levels will vary respectively. In any case, it is recom-
mended to limit the fan-out to one, in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
which provide the added benefit of isolating the A/D con-
verter from any digital activities on the bus from coupling
back high frequency noise and degrading the performance.
The standard output coding is Straight Offset Binary where
the full scale input signal corresponds to all “1”s at the
output (see Table I). The digital outputs of the ADS902 can
be set to a high impedance state by driving the OE (pin 16)
with a logic “H”. Normal operation is achieved with a “L”
at OE or left unconnected due to the internal pull-down
resistor.
3kΩ
1/2 A₁
10Ω
Bottom
Reference
(Pin 24)
R_F2
+V_S
+LV_DD
1,18, 28
ADS902
2
Digital
Output
Stage
R_G2
A₁ = OPA2237 or Equivalent.
FIGURE 8. Independent Supply Connection for Output
Stage.
FIGURE 7. Precise Solution to Supply External Reference
Voltages to the ADS902.
CLOCK INPUT
SINGLE-ENDED INPUT
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
The clock input of the ADS902 is designed to accommodate
+FS (IN = +3.25V)
1111111111
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support maximum sampling rates (30MSPS), high speed or
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
1111111111
1111111110
1110000000
1100000000
advanced CMOS logic should be used (HC/HCT, AC/ACT).
When digitizing at high sampling rates, a 50% duty cycle
along with fast rise and fall times (2ns or less) are recom-
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +2.75V)
–1LSB
1010000000
1000000001
1000000000
0111111111
mended to meet the rated performance specifications. How-
ever, the ADS902 performance is tolerant of duty-cycle
variations of as much as ±5%, which should not affect
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
0110000000
0100000000
0010000000
0000000001
performance. For applications operating with input frequen-
–FS (IN = +2.25V)
0000000000
cies up to Nyquist or undersampling applications, special
®
TABLE I. Coding Table for the ADS902.
ADS902
10