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EP9302 Datasheet, PDF (1/42 Pages) Cirrus Logic – High-speed ARM9 System-on-chip Processor with MaverickCrunch | |||
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EP9302 Data Sheet
FEATURES
⢠200-MHz ARM920T Processor
⢠16-kbyte Instruction Cache
⢠16-kbyte Data Cache
⢠Linux®, Microsoft® Windows® CE-enabled MMU
⢠100-MHz System Bus
⢠MaverickCrunch⢠Math Engine
⢠Floating point, Integer and Signal Processing
Instructions
⢠Optimized for digital music compression and
decompression algorithms.
⢠Hardware interlocks allow in-line coding.
⢠MaverickKey⢠IDs
⢠32-bit unique ID can be used for DRM-compliant,
128-bit random ID.
⢠Integrated Peripheral Interfaces
⢠16-bit SDRAM Interface (up to 4 banks)
⢠16-bit SRAM / FLASH / ROM
⢠Serial EEPROM Interface
⢠1/10/100 Mbps Ethernet MAC
⢠Two UARTs
⢠Two-port USB 2.0 Full-speed Host (OHCI)
(12 Mbits per second)
⢠IrDA Interface
⢠ADC
⢠Serial Peripheral Interface (SPI) Port
High-speed ARM9
System-on-chip Processor
with MaverickCrunch
⢠6-channel Serial Audio Interface (I2S)
⢠2-channel, Low-cost Serial Audio Interface (AC'97)
⢠Internal Peripherals
⢠12 Direct Memory Access (DMA) Channels
⢠Real-time Clock with Software Trim
⢠Dual PLL controls all clock domains.
⢠Watchdog Timer
⢠Two General-purpose 16-bit Timers
⢠One General-purpose 32-bit Timer
⢠One 40-bit Debug Timer
⢠Interrupt Controller
⢠Boot ROM
⢠Package
⢠208-pin LQFP
Serial
Audio
Interface
(2) UARTs
w/
IrDA
(2) USB
Hosts
Ethernet
MAC
http://www.cirrus.com
Peripheral Bus
12 Channel DMA
M averickK eyTM
Processor Bus
Boot
ROM
MaverickCrunchTM
ARM 920T
D-Cache I-Cache
16KB
16KB
MMU
Clocks &
Timers
Interrupts
& GPIO
Bus Bridge
SRAM &
Flash I/F
Unified
SDRAM I/F
MEMORY AND STORAGE
©Copyright 2005 Cirrus Logic (All Rights Reserved)
MAR â05
DS653PP3
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