CS8411 Datasheet, PDF (1/38 Pages) Cirrus Logic – DIGITAL AUDIO INTER FACE RECEIVER

CS8411
CS8412
Digital Audio Interface Receiver
Features
l Monolithic CMOS Receiver
l Low-Jitter, On-Chip Clock Recovery
256x Fs Output Clock Provided
l Supports: AES/EBU, IEC958, S/PDIF, &
EIAJ CP-340 Professional and Consumer
Formats
l Extensive Error Reporting
- Repeat Last Sample on Error Option
l On-Chip RS422 Line Receiver
l Configurable Buffer Memory (CS8411)
Description
The CS8411/12 are monolithic CMOS devices which re-
ceive and decode audio data according to the AES/EBU,
IEC958, S/PDIF, & EIAJ CP-340 interface standards.
The CS8411/12 receive data from a transmission line,
recover the clock and synchronization signals, and de-
multiplex the audio and digital data. Differential or single
ended inputs can be decoded.
The CS8411 has a configurable internal buffer memory,
read via a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.
The CS8412 de-multiplexes the channel, user, and va-
lidity data directly to serial output pins with dedicated
output pins for the most important channel status bits.
ORDERING INFORMATION
See page 32.
I
CS8411
VD+ DGND VA+ FILT AGND
7
8
22
20
21
MCK
19
9
RXP
RXN ¹⁰
RS422
Receiver
Clock and Data Recovery
De-MUX
CS8412
IEnable and Status
25
ERF
14
INT
VD+ DGND VA+ FILT AGND
7
8
22
20
21
MCK
19
9
RXP
RXN ¹⁰
RS422
Receiver
Clock and Data Recovery
De-MUX
MUX
13
16
CS12/ SEL
FCK
MUX
6 5 4 3 2 27
C0/ Ca/ Cb/ Cc/ Cd/ Ce/
E0 E1 E2 F0 F1 F2
Audio
Serial Port
Configurable
Buffer
Memory
26
SDATA
12 _SCK
11
FSYNC
13 _A4/FCK
4
A3-A0
8
D7-D0
24 _CS
23 _RD/WR
M3 M2 M1 M0
17 18 24 23
Audio
Serial Port
Registers
25 15
ERF CBL
26
SDATA
12
SCK
11 _FSYNC
1
14
C
U
28 _VERF
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1998
(All Rights Reserved)
OCT ‘98
DS61F1
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