CS61584A Datasheet, PDF (1/54 Pages) Cirrus Logic – DUAL T1/E1 LINE INTERFACE

CS61584A
CS61584A
DDuuaall TT11//EE11 LLiinnee IInntteerrffaaccee
Features
l Dual T1/E1 Line Interface
l 3.3 Volt and 5 Volt Versions
l Crystal-less Jitter Attenuator Meets
European CTR 12 and ETSI ETS 300 011
Specifications
l Matched Impedance Transmit Drivers
l Transmitter Tri-state Capability
l Common Transmit and
ReceiveTransformers for all Modes
l Serial and Parallel Host Mode Operation
l User-customizable Pulse Shapes
l Supports JTAG Boundary Scan
l Compliant with:
– ITU-T Recommendations: G.703, G.704,
G.706, G.732, G.775 and I.431
– American National Standards (ANSI): T1.102,
T1.105, T1.403, T1.408, and T1.231
– FCC Rules and Regulations: Part 68 and Part
15
– AT&T Publication 62411
– ETSI ETS 300 011, 300 233, CTR 12, TBR 13
l TR-NET-00499
Description
The CS61584A is a dual line interface for T1/E1 appli-
cations, designed for high-volume cards where low
power and high density are required. The device is op-
timized for flexible microprocessor control through a
serial or parallel Host mode interface. Hardware mode
operation is also available.
Matched impedance drivers reduce power consumption
and provide substantial transmitter return loss. The
transmitter pulse shapes are customizable to allow non-
standard line loads. Crystalless jitter attenuation com-
plies with most stringent standards. Support of JTAG
boundary scan enhances system testability and
reliability.
ORDERING INFORMATION
See page 53.
CS61584A-IQ3:3.3V, 64-pin TQFP, -40 to +85° C
CS61584A-IL5:5.0V, 68-pin PLCC, -40 to +85° C
CS61584A-IQ5:5.0V, 64-pin TQFP, -40 to +85° C
Serial Port
Parallel Port
Hardware Mode
IPOL P/S
CS
INT SCLK SDO SDI SPOL
IPOL (DTACK) P/S
CS
INT RD(DS) AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE(AS) WR(R/W) BTS
CLKE ATTEN0 ATTEN1 RLOOP1 RLOOP2 LLOOP TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22 CON31 CON32
TCLK1
(TDATA1) TPOS1
(AIS1) TNEG1
RCLK1
(RDATA1) RPOS1
(BPV1) RNEG1
TCLK2
(TDATA2) TPOS2
(AIS2) TNEG2
RCLK2
(RDATA2) RPOS2
(BPV2) RNEG2
E
N
C
O
D
E
R
D
E
C
O
D
E
R
E
N
C
O
D
E
R
D
E
C
O
D
E
R
JTAG
4
CONTROL
R
E
M
O
T
E
JITTER
L
O
ATTENUATOR
O
P
B
A
C
K
R
E
M
O
T
E
JITTER
L
O
ATTENUATOR
O
P
B
A
C
K
CLOCK GENERATOR
REFCLK XTALOUT 1XCLK
L
L
O
O
C
PULSE
C
A
TAOS
SHAPING
DRIVER
A
L
CIRCUITRY
L
L
L
O
O
O
O
P
P
B
LOS &
CLOCK &
B
A
AIS
DATA
RECEIVER
A
C
DETECT
RECOVERY
C
K
K
1
2
L
L
O
O
C
PULSE
C
A
TAOS
SHAPING
DRIVER
A
L
CIRCUITRY
L
L
L
O
O
O
O
P
P
B
LOS &
CLOCK &
B
A
AIS
DATA
RECEIVER
A
C
DETECT
RECOVERY
C
K
K
1
2
2
2
2
2
3
CONTROL
TV+ TGND RV+ RGND DV+ DGND AV+ AGND BGREF PD1 PD2 LOS1 LOS2
SAD4 SAD5 SAD6 SAD7
ZTX1 ZTX2 LOS1 LOS2
TTIP1
TRING1
RTIP1
RRING1
TTIP2
TRING2
RTIP2
RRING2
RESET
MODE
Hardware Mode
Parallel Port
Serial Port
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
hPt.tOp:.//Bwowxw1.7c8ir4ru7s,.Acoumstin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com
Copyright © CirrCusopLyorgigich,t I©ncC. 2ir0ru0s5Logic, Inc. 2000
(All Rights Rese(rAvelldR) ights Reserved)
JAN ‘01
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