CS61581 Datasheet, PDF (1/37 Pages) Cirrus Logic – T1/E1 Universal Line Interface

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T1/E1 Universal Line Interface
Features
l Provides T1 and E1, Long Haul and Short
Haul Line Interface
l Provides a QRSS Test Signal and Error
Detector
l Impedance Matching Line Driver Using a
Single Transformer
l Greater than 14 dB of Transmit Return Loss
Without Using External Resistors
l No Crystal Needed for Jitter Attenuation
l Meets AT&T 62411 and TBR 12/13 Jitter
Tolerance and Attenuation Requirements
l Meets ANSI T1.231B and ITU-T G.775
Requirements for LOS and AIS
l Meets the BS6450 Transmitter Short-Circuit
Requirements for E1 Applications
l Compliant with:
– ITU-T Recommendations: G.703, G.732,
G.775 and I.431
– American National Standards (ANSI): T1.102,
T1.105, T1.403, T1.408, and T1.231
– FCC Rules and Regulations: Part 68 and Part
15
– AT&T Publication 62411
– ETSI ETS 300 011, 300 233, TBR 12/13
– TR-NET-00499
Description
The CS61581 is a primary rate line interface unit capa-
ble of operation in both short haul (intraoffice) and long
haul applications. The CS61581 combines the com-
plete analog transmit and receive circuitry for a single,
full-duplex interface at T1 and E1 rates. The device is
pin and function compatible with the Level One LXT310
and LXT318 (the latter in the host mode only). The de-
vice can also replace LXT359 and LXT360. Enhanced
functionality is available through an extended register
set allowing short haul operation, custom pulse shape
generation, QRSS pattern generation, detection and er-
ror counting, and generation and detection of loop up
and loop down codes. The CS61581 features Crystal^®
low-power impedance-matched line drivers and crystal-
less jitter attenuation.
ORDERING INFORMATION
CS61581-IL 28-pin PLCC
CS61581-IP 28-pin PDIP
TCLK
TDATA/TPOS
UBS/TNEG
JASEL
E
2N
3
C
O
4
D
E
R
11
Q
R
S
S
JITTER
ATTEN
REMOTE
LOOPBACK
LOCAL
LOOPBACK
(DIGITAL)
RCLK
RDATA/RPOS
BPV/RNEG
D
8E
C
7O
6
D
E
R
JITTER
ATTEN
TRANSMIT
TIMING &
CONTROL
PULSE
SHAPING
CIRCUITRY
ROM / RAM
LINE DRIVERS
TAOS Enable
LBO Select
SERIAL
PORT
REGISTERS & CONTROL LOGIC
LOS/
NLOOP
Clear
TIMING
& DATA
RECOVERY
SH/LH
LLOOP
Enable
EQUALIZER
CONTROL
SH
LOCAL
LOOPBACK
(ANALOG)
SLICERS
& PEAK
DETECT
NOISE &
CROSSTALK
FILTERS
MAGNITUDE
EQUALIZER
AGC
13
TTIP
16
TRING
28
CLKE/TAOS
26
CS/RLOOP
27
SCLK/LLOOP
24
SDI/LBO1
25
SDO/LBO2
18
LATN
19
RTIP
20
RRING
23
INT/NLOOP
12
LOS
INBAND
NLOOP
& LOS
PROCESSOR
SH
RECEIVE
CLOCK
GENERATOR
1
MCLK
9
XTALIN
10
XTALOUT
5
21
22
14
15
MODE RV+ RGND TGND TV+
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
hPt.tOp:.//Bwowxw1.7c8ir4ru7s,.Acoumstin, Texas 78760
[phone] FAX: [phone]
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Copyright © CirrCusopLyorgigich,t I.ncC. 2ir0ru0s5Logic, Inc. 2000
(All Rights Rese(rAvelldR) ights Reserved)
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