CS5531 Datasheet, PDF (1/52 Pages) Cirrus Logic – 16 BIT AND 24 BIT ADCS WITH ULTRA LOW NOISE PGIA

CS5531/32/33/34
16-Bit and 24-Bit ADCs with Ultra Low Noise PGIA
Features
Chopper Stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x
500 pA Input Current with Gains >1
Delta-Sigma Analog-to-Digital Converter
Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits
Two or Four Channel Differential MUX
Scalable Input Span via Calibration
±5 mV to differential ±2.5V
Scalable V_REF Input: Up to Analog Supply
Simple three-wire serial interface
SPI^®and Microwire™ Compatible
Schmitt Trigger on Serial Clock (SCLK)
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
General Description
The CS5531/32/33/34 are highly integrated ∆Σ Analog-
to-Digital Converters (ADCs) which use charge-balance
techniques to achieve 16-bit (CS5531/33) and 24-bit
(CS5532/34) performance. The ADCs are optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.
To accommodate these applications, the ADCs come as
either two-channel (CS5531/32) or four-channel
(CS5533/34) devices and include a very low noise chop-
per-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and
64×. These ADCs also include a fourth order ∆Σ modu-
lator followed by a digital filter which provides twenty
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt Trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See page 48
VA+
C1
C2
VREF+ VREF-
VD+
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
MUX
(CS5533/34
SHOWN)
PGIA
1,2,4,8,16
32,64
DIFFERENTIAL
4^TH ORDER ∆Σ
MODULATOR
LATCH
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
CS
SDI
SDO
SCLK
VA-
A0/GUARD
A1
OSC1 OSC2
DGND
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com
© Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAR ‘02
DS289PP5
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