ADS852 Datasheet, PDF (1/5 Pages) Burr-Brown (TI) – 14-Bit, 65MHz Sampling ANALOG-TO-DIGITAL CONVERTER

®
ADS852
PRELIMINARY INFORMATION
SUBJECT TO CHANGE
WITHOUT NOTICE
TM _{14-Bit, 65MHz Sampling}
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q HIGH DYNAMIC RANGE:
High SFDR: 100dB at 20MHz f_IN
High SNR: 75dB at 20MHz f_IN
q PREMIUM TRACK/HOLD:
High Bandwidth: 1GHz
Low Jitter: 0.25pS rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
DESCRIPTION
The ADS852 is a high-dynamic range 14-bit, 65MHz
pipelined analog-to-digital converter. It includes a high-
bandwidth linear track/hold that gives excellent spurious
performance up to and beyond the Nyquist rate. This high-
bandwidth track/hold also has a low jitter of only 0.25pS
rms, leading to excellent SNR performance. The clock input
can accept a low level differential sine wave or square wave
signal down to 0.5Vp-p, further improving the SNR perfor-
mance. It also accepts a single-ended clock signal and has
flexible threshold levels.
The ADS852 has a 4Vp-p differential input range (2Vp-p x
2 inputs, +16dBm) for optimum signal-to-noise ratio. The
+V_S
ADS852
q FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
APPLICATIONS
q BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, NMT
q TEST INSTRUMENTATION
q CCD IMAGING
differential operation gives the lowest even-order harmonic
components. A lower input voltage of 3Vp-p or 2Vp-p can
also be selected using the internal references, further opti-
mizing SFDR. Alternatively, a single-ended input range can
be used by tying the IN input to the common-mode voltage
if desired.
The ADS852 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front end signal conditioning circuitry. It also employs
digital error correction techniques to provide excellent dif-
ferential linearity for demanding imaging applications. The
ADS852 is available in a small 48-lead TQFP package.
CLK
Timing Circuitry
CLK
2Vp-p
IN
T/H
2Vp-p
IN
14-Bit
Pipelined
A/D Core
Error
Correction
Logic
D0
3-State
Outputs
•••
D13
CM
(+2.5V)
Reference Ladder
and Driver
Reference and
Mode Select
OVR
REFT
V_REF SEL1 SEL2 REFB
OE VDRV
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©_{1998 Burr-Brown Corporation}
PDS-1442
Printed in U.S.A. June, 1998