ADS7868IDBVTG4 Datasheet, PDF (1/28 Pages) Burr-Brown (TI) – 1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE

BurrĆBrown Products
from Texas Instruments
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE
FEATURES
• Single 1.2-V to 3.6-V Supply Operation
• High Throughput
– 200/240/280KSPS for 12/10/8-Bit V_DD ≥ 1.6 V
– 100/120/140KSPS for 12/10/8-Bit V_DD ≥ 1.2 V
• ±1.5LSB INL, 12-Bit NMC (ADS7866)
• 71 dB SNR, –83 dB THD at f_IN = 30 kHz
(ADS7866)
• Synchronized Conversion with SCLK
• SPI Compatible Serial Interface
• No Pipeline Delays
• Low Power
– 1.39 mW Typ at 200 KSPS, V_DD = 3.6 V
– 0.39 mW Typ at 200 KSPS, V_DD = 1.6 V
– 0.22 mW Typ at 100 KSPS, V_DD = 1.2 V
• Auto Power-Down: 8 nA Typ, 300 nA Max
• 0 V to V_DD Unipolar Input Range
• 6-Pin SOT-23 Package
APPLICATIONS
• Battery Powered Systems
• Isolated Data Acquisition
• Medical Instruments
• Portable Communication
• Portable Data Acquisition Systems
• Automatic Test Equipment
DESCRIPTION
The ADS7866/67/68 are low power, miniature,
12/10/8-bit A/D converters each with a unipolar,
single-ended input. These devices can operate from a
single 1.6 V to 3.6 V supply with a 200-KSPS
throughput for ADS7866. In addition, these devices
can maintain at least a 100-KSPS throughput with a
supply as low as 1.2 V.
The sampling, conversion, and activation of digital
output SDO are initiated on the falling edge of CS.
The serial clock SCLK is used for controlling the
conversion rate and shifting data out of the converter.
Furthermore, SCLK provides a mechanism to allow
digital host processors to synchronize with the con-
verter. These converters interface with
micro-processors or DSPs through a high-speed SPI
compatible serial interface. There are no pipeline
delays associated with the device.
The minimum conversion time is determined by the
frequency of the serial clock input, SCLK, while the
maximum frequency of SCLK is determined by the
minimum sampling time required to charge the input
capacitance to 12/10/8-bit accuracy for the
ADS7866/67/68, respectively. The maximum
throughput is determined by how often a conversion
is initiated when the minimum sampling time is met
and the maximum SCLK frequency is used. Each
device automatically powers down after each conver-
sion, which allows each device to save power when
the throughput is reduced while using the maximum
SCLK frequency.
The converter reference is taken internally from the
supply. Hence, the analog input range for these
devices is 0 V to V_DD.
These devices are available in a 6-pin SOT-23
package and are characterized over the industrial
–40°C to 85°C temperature range.
REF/V_DD
12/10/8 BIT ADC
Comparator
VIN
+
_S/H
CDAC
SAR
Conversion
and
Control
Logic
CS
SCLK
SDO
GND
Micro-Power Miniature SAR Converter Family
RESOLUTION/SPEED
12-Bit
10-Bit
8-Bit
< 200 KSPS
ADS7866 (1.2 V_DD to 3.6 V_DD)
ADS7867 (1.2 V_DD to 3.6 V_DD)
ADS7868 (1.2 V_DD to 3.6 V_DD)
1 MSPS – 1.25 MSPS
ADS7886 (2.35 V_DD to 5.25 V_DD)
ADS7887 (2.35 V_DD to 5.25 V_DD)
ADS7888 (2.35 V_DD to 5.25 V_DD)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated