ATF-511P8 Datasheet, PDF (3/15 Pages) Agilent(Hewlett-Packard) – High Linearity Enhancement Mode

ATF-511P8 Electrical Specifications
T_A = 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 200 mA unless otherwise specified.
Symbol
Vgs
Vth
Idss
Gm
Igss
NF
G
OIP3
P1dB
PAE
ACLR
Parameter and Test Condition
Operational Gate Voltage
Threshold Voltage
Saturated Drain Current
Transconductance
Gate Leakage Current
Noise Figure ^[1]
Gain^[1]
Output 3^rd Order Intercept Point^[1,2]
Output 1dB Compressed^[1]
Power Added Efficiency
Adjacent Channel Leakage
Power Ratio^[1,3]
Vds = 4.5V, Ids = 200 mA
Vds = 4.5V, Ids = 32 mA
Vds = 4.5V, Vgs = 0V
Vds = 4.5V, Gm = Idss/Vgs;
Vgs = Vgs1 – Vgs2
Vgs1 = 0.55V, Vgs2 = 0.5V
Vds = 0V, Vgs = -4.5V
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
Offset BW = 5 MHz
Offset BW = 10 MHz
Units
Min.
Typ.
Max.
V
0.25
0.51
0.8
V
—
0.28
—
μA
—
16.4
—
mmho
—
2178
—
μA
-27
-2
—
dB
—
1.4
—
dB
—
1.2
—
dB
13.5
14.8
16.5
dB
—
17.8
—
dBm
38.5
41.7
—
dBm
—
43
—
dBm
28.5
30
—
dBm
—
29.6
—
%
52
68.9
—
%
—
68.6
—
dBc
—
-58.9
—
dBc
—
-62.7
—
Notes:
1. Measurements obtained using production test board described in Figure 6 and PAE tested at P1dB condition.
2. I ) 2 GHz OIP3 test condition: F1 = 2.0 GHz, F2 = 2.01 GHz and Pin = -5 dBm per tone.
II ) 900 MHz OIP3 test condition: F1 = 900 MHz, F2 = 910 MHz and Pin = -5 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
- Test Model 1
- Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
- Freq = 2140 MHz
- Pin = -5 dBm
- Channel Integrate Bandwidth = 3.84 MHz
4. Use proper bias, board, heatsink and derating designs to ensure maximum channel temperature is not exceeded. See absolute maximum
ratings and application note for more details.
Input
50 Ohm
Transmission
Line and
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.69
Γ_ang = -164°
(1.1 dB loss)
Output
Matching Circuit
DUT
Γ_mag = 0.65
Γ_ang = -163°
(0.9 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a trade-
off between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
3