BS616LV2020 Datasheet, PDF (9/11 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable

BSI
WRITE CYCLE2 ^(1,6)
ADDRESS
CE2
CE1
LB,UB
WE
D _OUT
D _IN
BS616LV2020
t WC
(11)
t CW
(5)
t AS
t BW
(5)
t AW
(4,10)
t WHZ
t WP
(2)
t WR ₍₃₎
t DH
(7)
(8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured± 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV2020
9
Revision 2.3
April 2002