BH616UV1611 Datasheet, PDF (5/12 Pages) Brilliance Semiconductor – Ultra Low Power/High Speed CMOS SRAM 1M X 16 bit / 2M x 8-bit

n DATA RETENTION CHARACTERISTICS (T_A = -40^OC to +85^OC)
BH616UV1611
SYMBOL
VDR
ICCDR
tCDR
tR
PARAMETER
TEST CONDITIONS
VCC for Data Retention
Data Retention Current
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VCC=1.2V
Chip Deselect to Data
Retention Time
See Retention Waveform
Operation Recovery Time
MIN.
1.0
--
0
tRC ⁽²⁾
TYP. ⁽¹⁾
--
1.5
--
--
MAX.
--
UNITS
V
15
uA
--
ns
--
ns
1. Typical characteristics are at TA=25^OC and not 100% tested.
2. tRC = Read Cycle Time.
n LOW V_CC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
VCC
CE1
VCC
tCDR
VIH
Data Retention Mode
VDR≧1.0V
CE1≧VCC - 0.2V
VCC
tR
VIH
n LOW V_CC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
VCC
VCC
tCDR
Data Retention Mode
VDR≧1.0V
CE2
CE2≦0.2V
VIL
VCC
tR
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
Output Load
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1,
tCHZ2, tBDO, tOHZ, tWHZ, tOW
Others
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
ALL INPUT PULSES
90%
10%
→←
Rise Time:
1V/ns
90%
10%
→←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
R0201-BH616UV1611
5
Revision 1.3
Otc.
2006