BS62UV2001 Datasheet, PDF (4/10 Pages) Brilliance Semiconductor – Ultra Low Power/Voltage CMOS SRAM 256K X 8 bit

BSI
BS62UV2001
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
2V
OUTPUT
1333 Ω
2V
OUTPUT
1333 Ω
INCLUDING
JIG AND
SCOPE
100PF
2000 Ω
INCLUDING
JIG AND
SCOPE
5PF
2000 Ω
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
800 Ω
1.2V
Vcc
GND
ALL INPUT PULSES
10%
→
90% 90%
←
→
FIGURE 2
10%
← 5ns
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0^oC to + 70^oC, Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t_AVQV
t _E1LQV
t
E2HOV
t_GLQV
t _E1LQX
t _E2HOX
t
GLQX
t _E1HQZ
t_E2HQZ
t_GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t_AA
t _ACS1
t
ACS2
t_OE
t _CLZ1
t _CLZ2
t
OLZ
t _CHZ1
t _CHZ2
t_OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
Output Disable to Output Address Change
BS62UV2001-70
MIN. TYP. MAX.
70
--
--
--
--
70
--
--
70
--
--
70
--
--
35
10
--
--
10
--
--
10
--
--
0
--
35
0
--
35
0
--
30
10
--
--
BS62UV2001-10
MIN. TYP. MAX.
100 --
--
--
-- 100
--
-- 100
--
-- 100
--
--
50
15
--
--
15
--
--
15
--
--
0
--
40
0
--
40
0
--
35
15
--
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS62UV2001
4
Revision 2.4
April 2002