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| BS616UV2019_08 Datasheet, PDF (4/11 Pages) Brilliance Semiconductor – Ultra Low Power CMOS SRAM 128K X 16 bit | |||
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 DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
VDR
ICCDR(3)
VCC for Data Retention
Data Retention Current
CEâ§VCC-0.2V or CE2(4)â¦0.2V,
VINâ§VCC-0.2V or VINâ¦0.2V
CEâ§VCC-0.2V or CE2(4)â¦0.2V,
VINâ§VCC-0.2V or VINâ¦0.2V
tCDR
tR
Chip Deselect to Data
Retention Time
Operation Recovery Time
See Retention Waveform
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCDR(Max.) is 0.7uA at TA=70OC.
4. 48B BGA ignore CE2 condition
 LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
VCC
CE
VCC
tCDR
VIH
Data Retention Mode
VDRâ§1.5V
CEâ§VCC - 0.2V
 LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
VCC
tCDR
Data Retention Mode
VDRâ§1.5V
CE2
CE2â¦0.2V
VIL
BS616UV2019
MIN. TYP. (1) MAX. UNITS
1.5
--
--
V
--
0.1
1.0
uA
0
--
tRC (2)
--
--
ns
--
ns
VCC
tR
VIH
VCC
tR
VIL
 AC TEST CONDITIONS
(Test Load and Input/Output Reference)
 KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Others
1V/ns
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
ALL INPUT PULSES
90%
10%
ââ
Rise Time:
1V/ns
90%
10%
ââ
Fall Time:
1V/ns
1. Including jig and scope capacitance.
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM âHâ TO âLâ
MAY CHANGE
FROM âLâ TO âHâ
DONâT CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE CHANGE
FROM âHâ TO âLâ
WILL BE CHANGE
FROM âLâ TO âHâ
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
âOFFâ STATE
R0201-BS616UV2019
4
Revision 1.4
Oct.
2008
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