BS616LV8015 Datasheet, PDF (4/9 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 512K X 16 bit

BSI
BS616LV8015
„ AC TEST CONDITIONS
„ KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
WAVEFORM
INPUTS
MUST BE
STEADY
OUTPUTS
MUST BE
STEADY
„ AC TEST LOADS AND WAVEFORMS
5.0V
OUTPUT
1928 Ω
5.0V
OUTPUT
1928 Ω
INCLUDING
JIG AND
SCOPE
100PF
1020 Ω
INCLUDING
JIG AND
SCOPE
5PF
1020 Ω
FIGURE 1A
OUTPUT
THEVENIN EQUIVALENT
667 Ω
FIGURE 1B
1.73V
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
ALL INPUT PULSES
Vcc
GND
10%
→
90% 90%
←
→
10%
← 5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70^oC, Vcc=5V)
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616LV8015-70
MIN. TYP. MAX.
t
AVAX
t
RC
Read Cycle Time
70 -- --
t
AVQV
t
AA
Address Access Time
-- -- 70
t
ELQV
t
ACS1
Chip Select Access Time
(CE1) _{-- -- 70}
t
ELQV
t
ACS2
Chip Select Access Time
(CE2) _{-- -- 70}
t
BA
t (1)
BA
Data Byte Control Access Time
(LB,UB) _--
-- 35
t
GLQV
t
OE
Output Enable to Output Valid
-- -- 35
t
ELQX
t
CLZ
Chip Select to Output Low Z (CE2,CE1) 10 -- --
t
BE
t
BE
Data Byte Control to Output Low Z (LB,UB) 10 -- --
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10 -- --
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z ^(CE2,CE1) 0
-- 35
t
BDO
t
BDO
Data Byte Control to Output High Z (LB,UB) 0
-- 35
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0 -- 30
t
AXOX
t
OH
Output Disable to Address Change
10 -- --
BS616LV8015-55
MIN. TYP. MAX.
55 -- --
-- -- 55
-- -- 55
-- -- 55
-- -- 30
-- -- 30
10 -- --
10 -- --
10 -- --
0 -- 30
0 -- 30
0 -- 25
10 -- --
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV8015
4
Revision 2.4
April 2002