BS616LV1611_08 Datasheet, PDF (4/11 Pages) Brilliance Semiconductor – Very Low Power CMOS SRAM 1M X 16 bit

„ DATA RETENTION CHARACTERISTICS (T_A = -40^OC to +85^OC)
SYMBOL
PARAMETER
TEST CONDITIONS
V_DR
I_CCDR⁽³⁾
t_CDR
t_R
V_CC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CE1≧V_CC-0.2V or CE2≦0.2V,
VIN≧V_CC-0.2V or VIN≦0.2V
CE1≧V_CC-0.2V or CE2≦0.2V,
VIN≧V_CC-0.2V or VIN≦0.2V
See Retention Waveform
1. V_CC=1.5V, T_A=25^OC and not 100% tested.
2. t_RC = Read Cycle Time.
3. I_CCDR(Max.) is 4.0uA at T_A=70^OC.
„ LOW V_CC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
V_CC
CE1
V_CC
t_CDR
V_IH
Data Retention Mode
V_DR≧1.5V
CE1≧V_CC - 0.2V
„ LOW V_CC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
V_CC
V_CC
t_CDR
Data Retention Mode
V_DR≧1.5V
CE2
CE2≦0.2V
V_IL
BS616LV1611
MIN. TYP. ⁽¹⁾ MAX. UNITS
1.5
--
--
V
--
0.8
8.0
uA
0
--
t_RC ⁽²⁾
--
--
ns
--
ns
V_CC
t_R
V_IH
V_CC
t_R
V_IL
„ AC TEST CONDITIONS
(Test Load and Input/Output Reference)
„ KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t_CLZ, t_OLZ, t_CHZ, t_OHZ, t_WHZ
Others
1V/ns
0.5Vcc
C_L = 5pF+1TTL
C_L = 30pF+1TTL
Output
1 TTL
C_L(1)
V_CC
GND
ALL INPUT PULSES
90%
10%
→←
Rise Time:
1V/ns
90%
10%
→←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
R0201-BS616LV1611
4
Revision 2.4
Oct.
2008