BS62LV8003 Datasheet, PDF (1/10 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 1M X 8 bit

BSI ^{Very Low Power/Voltage CMOS SRAM}
1M X 8 bit
BS62LV8003
„ FEATURES
• Wide Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max) at Vcc = 3V
-10 100ns (Max) at Vcc = 3V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
„ GENERAL DESCRIPTION
The BS62LV8003 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable(CE2) and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8003 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8003 is available in 44 pin TSOP2 and 48-pin BGA type.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
Vcc
TEMPERATURE RANGE
BS62LV8003EC
BS62LV8003BC
BS62LV8003EI
BS62LV8003BI
+0 ^O C to +70^O C 2.4V ~ 3.6V
-40 ^O C to +85^O C 2.4V ~ 3.6V
SPEED
( ns )
Vcc=3V
70 / 100
70 / 100
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( I CC, Max )
Vcc=3V
Vcc=3V
3uA
20mA
6uA
25mA
PKG TYPE
TSOP2-44
BGA-48-0810
TSOP2-44
BGA-48-0810
„ PIN CONFIGURATIONS
A4
1
A3
2
A2
3
A1
4
A0
5
CE1
6
NC
7
NC
8
DQ0
9
DQ1
10
VCC
11
GND
12
DQ2
13
DQ3
14
NC
15
NC
16
WE
17
A19
18
A18
19
A17
20
A16
21
A15
22
BS62LV8003EC
BS62LV8003EI
44
A5
43
A6
42
A7
41
OE
40
CE2
39
A8
38
NC
37
NC
36
DQ7
35
DQ6
34
GND
33
VCC
32
DQ5
31
DQ4
30
NC
29
NC
28
A9
27
A10
26
A11
25
A12
24
A13
23
A14
1
2
3
4
5
6
A
NC
OE
A0
A1
A2
CE2
B
NC
NC
A3
A4
CE1
NC
C
D0
NC
A5
A6
NC
D4
D
VSS
D1
A17
A7
D5
VCC
E
VCC
D2
VCC
A16
D6
VSS
F
D3
NC
A14
A15
NC
D7
„ FUNCTIONAL BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
Address
22
Input
Buffer
Row
Decoder
2048
Memory Array
2048 X 4096
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
4096
8
Column I/O
Write Driver
Sense Amp
8
512
Column Decoder
18
Address Input Buffer
A11A9 A8 A3 A2 A1 A0A10 A19
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV8003
1
Revision 2.4
April 2002