BS62LV4007 Datasheet, PDF (1/10 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 512K X 8 bit

BSI Very Low Power/Voltage CMOS SRAM
512K X 8 bit
BS62LV4007
„ FEATURES
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
„ DESCRIPTION
The BS62LV4007 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
2.0uA at 5.0V/25^oC and maximum access time of 55ns at 5.0V/85^oC.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV4007TC
BS62LV4007STC
BS62LV4007SC
BS62LV4007EC
BS62LV4007PC
BS62LV4007TI
BS62LV4007STI
BS62LV4007SI
BS62LV4007EI
BS62LV4007PI
OPERATING
Vcc
TEMPERATURE RANGE
SPEED
( ns )
55ns :4.5~5.5V
70ns :4.5~5.5V
+0 ^O C to +70 ^O C 4.5V ~ 5.5V 55 / 70
-40 ^O C to +85^O C 4.5V ~ 5.5V 55 / 70
POWER DISSIPATION
STANDBY
( I CCSB1 , Max )
Operating
( I CC , Max )
Vcc =5.0V
Vcc = 5.0V Vcc =5.0V
55ns
70ns
30uA
68mA
58mA
60uA
70mA
60mA
PKG
TYPE
TSOP- 32
STSOP-32
SOP -32
TSOP2 - 32
PDIP ^-32
TSOP - 32
STSOP - 32
SOP - 32
TSOP2- 32
PDIP - 32
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 BS62LV4007SC 25
9 ^BS62LV4007SI 24
10
11
BS62LV4007EC
BS62LV4007EI
BS62LV4007PC
23
22
12 _BS62LV4007PI 21
13
20
14
19
15
18
16
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A11 1
A9 2
A8 3
A13 4
WE 5
A17 6
A15 7
VCC 8
A18 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
BS62LV4007TC
BS62LV4007STC
BS62LV4007TI
BS62LV4007STI
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
WE
OE
Vdd
GND
Address
22
Input
Buffer
Row
Decoder
2048
Memory Array
2048 X 2048
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
2048
8
Column I/O
Write Driver
Sense Amp
8
256
Column Decoder
16
Address Input Buffer
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4007
1
Revision 1.1
Jan. 2004