BS616UV8010 Datasheet, PDF (1/9 Pages) Brilliance Semiconductor – Ultra Low Power/Voltage CMOS SRAM 512K X 16 bit

BSI ^{Ultra Low Power/Voltage CMOS SRAM}
512K X 16 bit
BS616UV8010
„ FEATURES
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade: 15mA (Max.) operating current
I-grade : 20mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc=2V
-10 100ns (Max.) at Vcc=2V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ DESCRIPTION
The BS616UV8010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616UV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8010 is available in 48-pin BGA package.
„ PRODUCT FAMILY
OPERATING
Vcc
PRODUCT FAMILY
TEMPERATURE RANGE
SPEED
(ns)
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC , Max)
Vcc=2 VVcc=2V Vcc=3V Vcc=2V Vcc=3V
PKG TYPE
BS616UV8010BC +0^OC to +70^OC 1.8V ~ 3.6V 70 / 100 2uA 3uA 15mA 20mA
BGA - ⁴⁸ -0810
BS616UV8010BI _- 40^O C to +85^OC 1.8V ~ 3.6V 70 / 100 4uA 6uA 20mA 25mA
BGA - ⁴⁸ -0810
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
1
2
3
4
5
6
A LB OE A0 A1 A2 CE2
B D8 UB A3 A4 CE1 D0
C D9 D10 A5 A6 D1 D2
D VSS D11 A17 A7 D3 VCC
E VCC ^D12 VSS ^{A16 D4} VSS
F D14 D13 A14 A15 ^{D5 D6}
G D15 N.C A12 A13 WE D7
H A18 A8 A9 A10 A11 NC
48-Ball CSP top View
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
D0
.
.
.
.
D15
Address
22
Input
Buffer
Row
2048
Decoder
Data
16
Input
16
.
Buffer
.
.
16
.
Data
Output
16
Buffer
Memory Array
2048 x 4096
4096
Column I/O
Write Driver
Sense Amp
256
Column Decoder
CE2
CE1
WE
OE
UB
LB
Vcc
Gnd
Control
16
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616UV8010
1
Revision 2.4
April 2002