BS616LV4017_06 Datasheet, PDF (1/11 Pages) Brilliance Semiconductor – Very Low Power CMOS SRAM 256K X 16 bit

Very Low Power CMOS SRAM
256K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616LV4017
n FEATURES
Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
Ÿ Very low power consumption :
VCC = 3.0V Operation current : 27mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.25uA (Typ.)at 25 ^OC
VCC = 5.0V Operation current : 65mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 1.5uA (Typ.) at 25^OC
Ÿ High speed access time :
-55 55ns(Max.) at VCC=3.0~5.5V
-70 70ns(Max.) at VCC=2.7~5.5V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V
n POWER CONSUMPTION
n DESCRIPTION
The BS616LV4017 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 by 16 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.25uA at 3.0V/25^OC and maximum access time of 55ns at
3.0V/85^OC.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV4017 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV4017 is available in DICE form, JEDEC standard
44-pin TSOP II and 48-ball BGA package.
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
(ICCSB1, Max)
VCC=5.0V VCC=3.0V
BS616LV4017DC
BS616LV4017AC
BS616LV4017EC
Commercial
+0^OC to +70^OC
10uA
2.0uA
BS616LV4017AI
BS616LV4017EI
Industrial
-40^OC to +85^OC
20uA
4.0uA
POWER DISSIPATION
1MHz
VCC=5.0V
10MHz
Operating
(ICC, Max)
fMax.
1MHz
VCC=3.0V
10MHz
9mA 39mA 63mA 1.5mA 14mA
10mA 40mA 65mA 2mA 15mA
fMax.
26mA
27mA
PKG TYPE
DICE
BGA-48-0608
TSOP II-44
BGA-48-0608
TSOP II-44
n PIN CONFIGURATIONS
A4 1
44 A5
A3 2
43 A6
A2 3
42 A7
A1 4
41 OE
A0 5
40 UB
CE 6
39 LB
DQ0 7
38 DQ15
DQ1 8
37 DQ14
DQ2 9
36 DQ13
DQ3 10
35 DQ12
VCC 11 BS616LV4017EC 34 VSS
VSS 12 _{BS616LV4017EI}
DQ4 13
33 VCC
32 DQ11
DQ5 14
31 DQ10
DQ6 15
30 DQ9
DQ7 16
29 DQ8
WE 17
28 NC
A17 18
27 A8
A16 19
26 A9
A15 20
25 A10
A14 21
24 A11
A13 22
23 A12
1
2
3
4
5
6
A
LB OE A0 A1 A2 NC
B
D8 UB A3 A4 CE D0
C
D9 D10 A5 A6 D1 D2
D VSS D11 A17 A7 D3 VCC
E VCC D12 NC A16 D4 VSS
F
D14 D13 A14 A15 D5 D6
G D15 NC A12 A13 WE D7
H
NC A8 A9 A10 A11 NC
n BLOCK DIAGRAM
A12
A11
A10
A9
A8
A5
A6
A7
A4
A3
DQ0
.
.
.
.
.
.
DQ15
CE
WE
OE
UB
LB
VCC
VSS
Address
10
Input
Buffer
16
.
.
.
.
16
.
.
Control
Row
Decoder
1024
Memory Array
1024 x 4096
Data
Input
16
Buffer
Data
16
Output
Buffer
4096
Column I/O
Write Driver
Sense Amp
256
Column Decoder
8
Address Input Buffer
A13 A14 A15 A16 A17 A0 A1 A2
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4017
1
Revision 1.3
May.
2006