BS616LV2025 Datasheet, PDF (1/11 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable

BSI Very Low Power/Voltage CMOS SRAM
128K x 16 or 256K x 8 bit switchable _BS616LV2025
„ FEATURES
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 5.0V
-55 55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
„ DESCRIPTION
The BS616LV2025 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits or
262,144 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/55 ns in 5V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV2025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2025 is available in DICE form and 48-pin BGA type.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2025DC
BS616LV2025AC
BS616LV2025DI
BS616LV2025AI
OPERATING
TEMPERATURE
Vcc
RANGE
+0 ^O C to +70 ^O C 4.5V ~ 5.5V
-40 ^O C to +85 ^O C 4.5V ~ 5.5V
SPEED
( ns )
Vcc=5.0V
70 / 55
70 / 55
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC, Max )
Vcc=5.0V
Vcc=5.0V
6uA
40mA
25uA
45mA
PKG TYPE
DICE
BGA-48-0608
DICE
BGA-48-0608
„ PIN CONFIGURATION
„ BLOCK DIAGRAM
A15
A14
A13
A12
Address
A11
20
1024
A10
Input
Row
A9
Buffer
A8
Decoder
A7
A6
D0
.
.
.
.
.
.
.
.
D15
16(8)
16(8)
Data
Input
Buffer
16(8)
16(8)
Data
Output
Buffer
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128(256)
Column Decoder
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
Vss
Control
14(16)
Address Input Buffer
A16 A0 A1 A2 A3 A4 A5 _(SAE)
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2025
1
Revision 2.4
April 2002