BS616LV2013 Datasheet, PDF (1/11 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 128K X 16 bit

B S I ^{Very Low Power/Voltage CMOS SRAM}
128K X 16 bit
BS616LV2013
„ FEATURES
„ DESCRIPTION
• Very low operation voltage : 2.4 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
-10 100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ PRODUCT FAMILY
The BS616LV2013 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2013 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2013 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package , JEDEC standard 48-pin TSOP Type I package
and 48-ball BGA package.
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
Vcc=3.0V
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC, Max )
Vcc=3.0V
Vcc=3.0V
PKG TYPE
BS616LV2013DC
BS616LV2013EC
BS616LV2013TC
BS616LV2013AC
BS616LV2013DI
BS616LV2013EI
BS616LV2013TI
BS616LV2013AI
+0 ^O C to +70 ^O C
-40 ^O C to +85 ^O C
„ PIN CONFIGURATIONS
2.4V ~3.6V
2.4V ~ 3.6V
70/100
0.7uA
70/100
1.5uA
„ BLOCK DIAGRAM
20mA
25mA
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
1
44
A5
2
43
A6
3
42
A7
4
41
OE
5
40
UB
6
39
LB
7
38
DQ15
8
37
DQ14
9
36
DQ13
10 _{BS616LV2013EC} 35 _DQ12
11
12 BS616LV2013EI
34
GND
33
VCC
13
32
DQ11
14
31
DQ10
15
30
DQ9
16
29
DQ8
17
28
NC
18
27
A8
19
26
A9
20
25
A10
21
24
A11
22
23
NC
2
3
4
5
6
A
LB
OE
A0
A1
A2
N.C.
B
D8
UB
A3
A4
CE
D0
C
D9
D10
A5
A6
D1
D2
D
VSS D11 N.C.
A7
D3
VCC
E
VCC
D12
N.C.
A16
D4
VSS
F
D14 D13 A14
A15
D5
D6
A8
A13
A15
Address
A16
20
1024
A14
Input
A12
A7
Buffer
Row
Decoder
A6
A5
A4
16
DQ0
.
.
Data
Input
16
Buffer
.
.
.
.
16
.
.
Data
Output
16
DQ15
Buffer
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
G
D15 N.C. A12
A13
WE
D7
H
N.C.
A8
A9
A10
A11 N.C.
Brillia⁴n^8-c^bae^{ll B}S^Ge^Am^topi^vc^ieo^w nductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2013
1
Revision 2.5
April 2002