BS616LV1010_08 Datasheet, PDF (1/11 Pages) Brilliance Semiconductor – Very Low Power CMOS SRAM 64K X 16 bit

Very Low Power CMOS SRAM
64K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616LV1010
„ FEATURES
y Wide V_CC operation voltage : 2.4V ~ 5.5V
y Very low power consumption :
V_CC = 3.0V Operation current : 25mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.5/1.5uA (Max.) at 70/85^OC
V_CC = 5.0V Operation current : 45mA (Max.) at 55ns
5mA (Max.) at 1MHz
Standby current : 3/5uA (Max.) at 70/85^OC
y High speed access time :
-55
55ns(Max.) at V_CC=2.7~5.5V
-70
70ns(Max.) at V_CC=2.4~5.5V
y Automatic power down when chip is deselected
y Easy expansion with CE and OE options
y I/O Configuration x8/x16 selectable by LB and UB pin.
y Three state outputs and TTL compatible
y Fully static operation
y Data retention supply voltage as low as 1.5V
„ POWER CONSUMPTION
„ DESCRIPTION
The BS616LV1010 is a high performance, very low power CMOS
Static Random Access Memory organized as 65,536 by 16 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
current of 1.5/5uA at Vcc=3/5V at 85^OC and maximum access time
of 55/70ns.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV1010 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV1010 is available in DICE form, JEDEC standard
44-pin TSOP II and 48-ball BGA package.
PRODUCT
FAMILY
OPERATING
STANDBY
TEMPERATURE
(I_CCSB1, Max)
V_CC=5.0V V_CC=3.0V
BS616LV1010DC
BS616LV1010AC
BS616LV1010EC
Commercial
+0^OC to +70^OC
3.0uA
0.5uA
BS616LV1010AI
BS616LV1010EI
Industrial
-40^OC to +85^OC
5.0uA
1.5uA
POWER DISSIPATION
1MHz
V_CC=5.0V
10MHz
Operating
(I_CC, Max)
f_Max.
1MHz
V_CC=3.0V
10MHz
4mA 24mA 44mA 1.5mA 14mA
5mA 25mA 45mA 2mA 15mA
f_Max.
24mA
25mA
PKG TYPE
DICE
BGA-48-0608
TSOP II-44
BGA-48-0608
TSOP II-44
„ PIN CONFIGURATIONS
A4 1
44 A5
A3 2
43 A6
A2 3
42 A7
A1 4
41 OE
A0 5
40 UB
CE 6
39 LB
DQ0 7
38 DQ15
DQ1 8
37 DQ14
DQ2 9
36 DQ13
DQ3 10
35 DQ12
VCC 11 BS616LV1010EC 34 VSS
VSS 12 _{BS616LV1010EI}
DQ4 13
33 VCC
32 DQ11
DQ5 14
31 DQ10
DQ6 15
30 DQ9
DQ7 16
29 DQ8
WE 17
28 NC
A15 18
27 A8
A14 19
26 A9
A13 20
25 A10
A12 21
24 A11
NC 22
23 NC
1
2
3
4
5
6
A
LB OE A0 A1 A2 NC
B
D8 UB A3 A4 CE D0
C
D9 D10 A5 A6 D1 D2
D VSS D11 NC A7 D3 VCC
E VCC D12 NC NC D4 VSS
F
D14 D13 A14 A15 D5 D6
G D15 NC A12 A13 WE D7
H
NC A8 A9 A10 A11 NC
48-ball BGA top view
„ BLOCK DIAGRAM
A8
A13
A15
A14
A12
A7
A6
A5
A4
DQ0
.
.
.
.
.
.
DQ15
CE
WE
OE
UB
LB
VCC
VSS
Address
9
Input
Buffer
16
.
.
.
.
16
.
.
Control
512
Row
Decoder
Memory Array
512 x 2048
Data
Input
16
Buffer
16
Data
Output
Buffer
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
7
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS616LV1010
1
Revision 2.7
Oct.
2008