HS-2605_1 Datasheet, PDF (28/82 Pages) BOSER Technology Co., Ltd – EDEN Embedded Engine Board

Connector JP3 Orientation
SPEAKER
RST_SW
HD_LED
12
34
56
78
9 10
11 12
13 14
15 16
CN25: External Reset Button
PIN Description
1
Reset
2
GND
PWR LED
EXT_SMI
PWR button
SLP button
1
2
3.19 Watchdog Timer
There are three access cycles of Watch-Dog Timer as Enable, Refresh
and Disable. The Enable cycle proceeds via READ PORT 443H
whereas the Disable cycle proceeds via READ PORT 045H. A
continued Enable cycle after a first Enable cycle means Refresh.
Once the Enable cycle is active, a Refresh cycle is requested before
the time-out period. This restarts counting of the WDT period. When
the time counting goes over the preset period of WDT, it will assume
that the program operation is abnormal. A System Reset signal to
re-start or a NMI cycle to the CPU transpires when such error happens.
Jumper JP1 is used to select the function of Watchdog Timer.
JP1: Watchdog Timer Active Type Setting
Options
Settings
Active NMI
Short 1-2 ¹
3
System Reset
Short 2-3
Disabled WDT (default)
Open
22