LM3S600 Datasheet, PDF (15/378 Pages) Bookham, Inc. – Microcontroller

LM3S600 Microcontroller
About This Document
This data sheet provides reference information for the LM3S600 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® CoreSight Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 15.
Table 1. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 34.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
October 01, 2007
15
Preliminary