MGA-655T6 Datasheet, PDF (4/14 Pages) AVAGO TECHNOLOGIES LIMITED – Low Noise Amplifier

Demo Board Layout
Part Size Value P/N
L1 0402 1.2 nH LLP1005 Series (TOKO)
L2 0402 1.0 nH LLP1005 Series (TOKO)
L3 0402 10.0 nH LLP1005 Series (TOKO)
C2 0402 4.7 pF C1005C0G1H4R7C (TDK)
C3 0402 4.7 pF C1005C0G1H4R7C (TDK)
C4 0402 0.1 uF MCH155 Series (Rohm)
C5 0402 1000 pF MCH155 Series (Rohm)
R1 0402 5.1 ohm MCR Series (Rohm)
J1* 0402 0 ohm RK73Z1E000 (KOA)
J2*,
Copper Foil
J3*
*Jumpers indicated in the demo board drawing are not
needed in actual application board; this is because generic
demo boards were used for development.
Figure 4. Demo board layout diagram*
*Application Notes:
1. Performance in a specified frequency band can be optimized by changing component values in the demoboard above to suit the application at
that frequency. The following graphs show components used to demonstrate performance at the (3 - 4) GHz band.
2. Operational Logic of Bypass pin (Pin 1):
- Normal LNA operation: [2 to 2.7] volt,
- Bypass mode: [0 to 0.2] volt
Pin 1 voltage in LNA mode can be varied to enable the LNA bias current to be adjusted.
Demo Board Schematic for 3.5 GHz Application
1
V_BYPASS
C5
RF_IN
2
L1
3
MGA 655T6
BIAS/CONTROL
6 _NC
5
C2
4
L2
Notes:
1. L1 is an input matching inductor.
2. L2 and C2 form the output matching
network.
3. R1&L3 is a network that isolates the
measurement demoboard from external
disturbances. C4 and C5 migrate the
RF_OUT
effect of external noise pickup on the
R1
Vdd and Vbypass lines. These components
are not required in actual operation.
4. C3 is a RF bypass capacitor.
L3
V_DD
C3
C4
Figure 5. Demo board schematic diagram
4