ACPL-5160 Datasheet, PDF (34/36 Pages) AVAGO TECHNOLOGIES LIMITED – 2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback

ACPL-5160 and ACPL-5161
Data Sheet
Junction Temperature Calculation
Assume maximum power dissipation, Pmax(buffer) = 0.15W,
Pmax(detector) = 0.6 W, P(LED) ~ 0.02W. If the ambient
temperature is 125°C, the calculated junction temperature for a
high conductivity board is:
T2 = (R₂₁ × P₁ + R₂₂ × P₂ + R₂₃ × P₃ + R₂₄ × P₄) + T_a
= (24 × 0.02 + 66 × 0.15 + 30 × 0.02 + 23 × 0.6) + 125 ~ 150°C
T4 = (R₄₁ × P₁ + R₄₂ × P₂ + R₄₃ × P₃ + R₄₄ × P₄) + T_a
= (27 × 0.02 + 26 × 0.15 + 26 × 0.02 + 35 × 0.6) + 125 ~ 150°C
NOTE
 The junction temperatures of the input and
output IC is ~150°C when operating at 125°C.
 No power derating is required when operating
below 125°C using a high conductivity board.
If low conductivity board is used, the calculated junction
temperature is:
T2 = (R₂₁ × P₁ + R₂₂ × P₂ + R₂₃ × P₃ + R₂₄ × P₄) + T_a
= (41 × 0.02 + 70 × 0.15 + 47 × 0.02 + 30 × 0.6) + 125 ~ 155°C
T4 = (R₄₁ × P₁ + R₄₂ × P2 + R₄₃ × P₃ + R₄₄ × P₄) + T_a
= (41 × 0.02 + 35 × 0.15 + 40 × 0.02 + 38 × 0.6) + 125 ~ 155°C
NOTE
 The junction temperatures of the input and
output IC exceeded the absolute maximum
junction temperature of 150°C.
 Power derating is required so that the junction
temperatures do not exceed 150°C.
 Output IC power dissipation is derated linearly at
20 mW/°C above 120°C.
 Input IC power dissipation is derated linearly at
5 mW/°C above 120°C.
System Considerations
Propagation Delay Difference (PDD)
The ACPL-516x includes a Propagation Delay Difference (PDD)
specification intended to help designers minimize dead time in
their power inverter designs. Dead time is the time period
during which both the high and low side power transistors (Q1
and Q2 in Figure 61) are off. Any overlap in Q1 and Q2
conduction results in large currents flowing through the power
devices between the high and low voltage motor rails, a
potentially catastrophic condition that must be prevented.
To minimize dead time in a given design, the turn-on of the
ACPL-516x driving Q2 should be delayed (relative to the
turn-off of the ACPL-516x driving Q1) so that under worst-case
conditions, transistor Q1 has just turned off when transistor Q2
turns on, as shown in Figure 80. The amount of delay necessary
to achieve this condition is equal to the maximum value of the
propagation delay difference specification, PDD_MAX, which is
specified to be 400 ns over the operating temperature range of
–55°C to +125°C.
Figure 80 Minimum LED Skew for Zero Dead Time
VIN+1
VOUT1
Q1 ON
Q1 OFF
VOUT2
Q2 OFF
Q2 ON
VIN+2
tPHLMAX
tPLHMIN
PDD* MAX = (tPHL - tPLH)MAX = tPHLMAX - tPLHMIN
*PDD = PROPAGATION DELAY
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Broadcom
- 34 -