BCM8727BIFBG Datasheet, PDF (2/2 Pages) Broadcom Corporation. – DUAL-CHANNEL 10-GBE SFI-TO-XAUI™ TRANSCEIVER WITH EDC

OVERVIEW
XAOP
XAON
XDOP
XDON
156.25 MHz
REFCLKP
REFCLKN
XAIP
XAIN
XDIP
XDIN
XAOP
XAON
XDOP
XDON
Serializer
Serializer
8B/10B
Encoder
8B/10B
Encoder
156.25M
CMU
64/66B
Synchronizer
Descrambler
Decoder
CDR and
Deserializer
322.26M
312.5M
MMF EDC
AGC
DSP Core
PDIP
PDIN
REFCK RefClk
Block
312.5M
DLL and
Deserializer
Sync. Detect
Lane Sync
8B/10B
Decoder
DLL and
Deserializer
Sync. Detect
Lane Sync
8B/10B
Decoder
Lane
Alignment
FIFO
Lane
Alignment
FIFO
64/66B
Encoder
Scrambler
312.5M
322.26M
CMU and
Serializer
32K
ROM uC
16K
RAM
SPI
SPI
PDOP
PDON
Serializer
Serializer
8B/10B
Encoder
8B/10B
Encoder
156.25M
CMU
64/66B
Synchronizer
Descrambler
Decoder
CDR and
Deserializer
322.26M
312.5M
MMF EDC
AGC
DSP Core
PDIP
PDIN
XAIP
XAIN
XDIP
XDIN
REFCK RefClk
Block
312.5M
DLL and
Deserializer
Sync. Detect
Lane Sync
8B/10B
Decoder
DLL and
Deserializer
Sync. Detect
Lane Sync
8B/10B
Decoder
Lane
Alignment
FIFO
Lane
Alignment
FIFO
MDIO
MDC
PRTAD[4:1]
RSTB
LASI
SDA
SCL
Management
and
Control
Interface
BSC Serial
Interface
JTAG
64/66B
Encoder
Scrambler
312.5M
322.26M
CMU and
Serializer
32K
ROM uC
16K
RAM
SPI
SPI
PDOP
PDON
Optics
Control
and
Status
OPRXLOS
MOD_ABS
OPTXENB
OPRSTB
BCM8727 Block Diagram
The BCM8727 is a dual-channel 10-GbE SFI-to-XAUI transceiver that
incorporates an Electronic Dispersion Compensation (EDC) equalizer
supporting SFP+ line-card applications.
The BCM8727 is a multirate PHY targeted for SMF, MMF, or copper
twin-ax applications interfacing to both limiting-based and linear-based
SFP+ and SFP modules. The BCM8727 is fully compliant to the 10-GbE
IEEE 802.3aq standard and also supports 1000BASE-X for 1-GbE
operation.
The BCM8727 is developed using an all-DSP high-speed front-end
providing the highest performance and most flexibility for line-card
designers. An on-chip microcontroller implements the control algorithm
for the DSP core.
On-chip clock synthesis is performed by the high-frequency, low-jitter,
Phase-Locked Loops (PLLs) for the PMD and XAUI output retimers.
Individual PMD and XAUI clock recovery is performed on the device by
synchronizing directly to the respective incoming data streams. An
external 156.25 MHz reference clock input is required for each port.
The BCM8727 Ethernet LRM PHY device is a fully integrated SerDes
(10.3125 Gbps) interface device performing the extension functions for
a 10-Gigabit serial Ethernet Reconciliation Sublayer (RS) interface. The
XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B
coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data
Recovery (CDR).
The BCM8727 is available in a 19 mm x 19 mm, 1 mm pitch, 324-pin
BGA, RoHS-compliant package. The BCM8727 supports a footprint-
compatible layout with the BCM8726 dual LRM PHY.
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®
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8727-PB00-R
03/16/09
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