BCM3212 Datasheet, PDF (2/2 Pages) Broadcom Corporation. – DOCSIS-TM 1.1 ADVANCED CMTS MAC

OVERVIEW
Upstream
SDRAM 1
Upstream
SDRAM 2
BCM3212
U p s tre a m
PHY i/f
DES
decrypt
Request
filte rin g
Burst
DMA
SDRAM
co n tro lle r
Post-Processing
Payload
Deconcatenation Header
Expand
Packet
DMA
Fragment
reassem bly
controller
Request
DMA
O ut-of-
band
PHY
Interface
Downstream
PHY
Interface
MAP
parser
Tim estam p
generation
MPEG
encapsulate
MAP
filte rin g
Out-of-
band
Generator
In-band DOCSIS Processor
DES
Encrypt
DOCSIS
Header
creator
Payload
Header
Suppress
Out-of-
band
queue
DMA
In-band
queue
DMA
SDRAM
controller
Output
queue
manager
100/1000
Ethernet
MAC
Input
Queue
manager
PCI Bus
Interface
Unit
SDRAM
controller
Downstream
SDRAM
The BCM3212 is a highly integrated CMTS MAC IC for use in
DOCSIS^TM 1.1 and advanced TDMA PHY-layer CMTS products. With
hardware support for concatenation parsing, fragment reassembly,
payload header suppression, and advanced TDMA PHY-layer data rates,
the BCM3212 serves as the heart of a next-generation CMTS. The
BCM3212 provides a powerful, yet cost-effective solution for a variety
of CMTS architectures.
The BCM3212 is based on sophisticated hardware processing engines
for both the upstream and downstream paths. To achieve upstream
throughput of 200 000 packets per second, the upstream processor design
is segmented and uses two banks of SDRAM to minimize latency on the
internal buses. The Upstream Processor performs DES decryption,
fragment reassembly, deconcatenation, payload header expansion,
PROPANE^TM packet acceleration, upstream MIB statistic gathering,
and priority queuing for the resultant packets. Each upstream queue can
be independently configured to output packets to either the PCI or GMII
interface. DOCSIS MAC management messages and bandwidth requests
are extracted and queued separately from data packets so that they are
readily available to the system controller.
The downstream processor accepts packets from priority queues and
performs payload header suppression, DOCSIS header creation, DES
encryption, CRC and HCS generation, MPEG encapsulation and
multiplexing, and timestamp generation on the in-band data. The
BCM3212 also includes an out-of-band generator and TDMA PHY
interface so that the BCM3212 can communicate with the out-of-band
receiver of the BCM3352 cable modem device for control of power
management functions.
All configuration and management of the BCM3212 is done via the PCI
interface. The PCI interface accommodates either 32-bit or 64-bit hosts
operating at either 33 MHz or 66 MHz. The 100/1000 Ethernet MAC
provides a standard interface (IEEE 802.3z GMII or MII) for
transporting packets to and from the BCM3212.
A single BCM3212 supports the association of 1 downstream channel
with up to 6 upstream channels. By connecting multiple BCM3212 chips
via the seamless master/slave interface, many other ratios may be
achieved, including 2 downstream to 12 upstream (2:12) and 1
downstream to 24 upstream (1:24). In multiple downstream
configurations, upstream channels can be remotely provisioned to be
associated with 1 of 2 downstream channels to enable load shifting.
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BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
3212-PB04-R
07/01/04
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