ATF-55143 Datasheet, PDF (15/20 Pages) AVAGO TECHNOLOGIES LIMITED – Low Noise Enhancement Mode Pseudomorphic HEMT

The values of resistors R1 and R2 are calculated with the
following formulas
R1 = ^{Vgs (2)}
I^p
BB
R2 = ^{(Vds – Vgs) R1 (3)}
V
p
gs
Example Circuit
V = 3V
DD
V = 2.7V
ds
I = 10 mA
ds
V = 0.47 V
gs
Choose I to be at least 10X the normal expected gate
BB
leakage current. I was conservatively chosen to be
BB
0.5 mA for this example. Using equations (1), (2), and (3)
the resistors are calculated as follows
R1 = 940Ω
R2 = 4460Ω
R3 = 28.6Ω
Active Biasing
Active biasing provides a means of keeping the quies-
cent bias point constant over temperature and constant
over lot to lot variations in device dc performance. The
advantage of the active biasing of an enhancement
mode PHEMT versus a depletion mode PHEMT is that a
negative power source is not required. The techniques
of active biasing an enhancement mode device are very
similar to those used to bias a bipolar junction transis-
tor.
INPUT
C1
Q1
Zo
L1
L2
C2
R5
C3
R6
C7
Q2
R7
R1
C4
OUTPUT
Zo
L4
L3
C5
R4
C6
Vdd
R3
R2
Figure 34. Typical ATF-55143 LNA with Active Biasing.
An active bias scheme is shown in Figure 34. R1 and R2
provide a constant voltage source at the base of a PNP
transistor at Q2. The constant voltage at the base of Q2
is raised by 0.7 volts at the emitter. The constant emitter
voltage plus the regulated V supply are present across
DD
resistor R3. Constant voltage across R3 provides a con-
stant current supply for the drain current. Resistors R1
and R2 are used to set the desired Vds. The combined
15
series value of these resistors also sets the amount of
extra current consumed by the bias network. The equa-
tions that describe the circuit’s operation are as follows.
V
E
=
V
ds
+
(I
ds
•
R4)
(1)
V –V
R3 = ^{DD E}
(2)
I
p
ds
V =V –V
(3)
B
E BE
R1
(4)
V=
V
B _{R1 + R2p} DD
V = I (R1 + R2) (5)
DD BB
Rearranging equation (4) provides the following for-
mula
R (V – V )
R2 = ^{1 DD B}
(4A)
V
B
and rearranging equation (5) provides the following
formula
V
R1 =
DD
(5A)
( )⁹
I_BB
1+
V –V
DD B
p
V
B
Example Circuit
V = 3V
DD
V = 2.7V
ds
I = 10 mA
ds
R4 = 10Ω
I = 0.5 mA
BB
V = 0.7 V
BE
Equation (1) calculates the required voltage at the emit-
ter of the PNP transistor based on desired V and I
ds
ds
through resistor R4 to be 2.8V. Equation (2) calculates
the value of resistor R3 which determines the drain cur-
rent I . In the example R3 = 20Ω. Equation (3) calculates
ds
the voltage required at the junction of resistors R1 and
R2. This voltage plus the step-up of the base emitter
junction determines the regulated V . Equations (4) and
ds
(5) are solved simultaneously to determine the value
of resistors R1 and R2. In the example R1=4200Ω and
R2 =1800Ω. R7 is chosen to be 1kΩ. This resistor keeps
a small amount of current flowing through Q2 to help
maintain bias stability. R6 is chosen to be 10kΩ. This
value of resistance is necessary to limit Q1 gate current
in the presence of high RF drive levels (especially when
Q1 is driven to the P gain compression point). C7
1dB
provides a low frequency bypass to keep noise from Q2
effecting the operation of Q1. C7 is typically 0.1 μF.