ACPL-M21L Datasheet, PDF (11/16 Pages) AVAGO TECHNOLOGIES LIMITED – Low Power, 5 MBd Digital CMOS Optocoupler

ACPL-M21L, ACPL-021L, ACPL-024L, ACPL-W21L, ACPL-K24L
Data Sheet
Switching Specifications (AC)
Over recommended temperature (T_A = –40°C to +105°C), supply voltage (2.7V ≤ V_DD ≤ 5.5V). All typical specifications are at
V_DD = 2.7V, T_A = 25°C.
Table 8 Switching Specifications (AC)
Parameter
Symbol
Propagation Delay Time to Logic Low t_PHL
Output^a
Propagation Delay Time to Logic
t_PLH
High Output^a
Pulse Width Distortion^b
PWD
Propagation Delay Skew^c
t_PSK
Output Rise Time (10% to 90%)
t_R
Output Fall Time (90% to 10%)
tF
Min.
Static Common Mode Transient
|CM_H|
25
Immunity at Logic High Output^d
Static Common Mode Transient
|CM_L|
25
Immunity at Logic Low Output^e
Typ.
130
115
11
11
40
40
Max.
250
250
200
220
Units
Test Conditions
ns
I_F=2.2 mA, C_L=15 pF (Figure 13,
Figure 17), CMOS Signal Levels
ns
I_F=2.2 mA, C_L=15 pF (Figure 14,
Figure 17), CMOS Signal Levels
ns
CMOS Signal Levels
ns
ns
ns
kV/μs
kV/μs
I_F = 2.2 mA, C_L= 15 pF,
CMOS Signal Levels.
I_F = 2.2 mA, C_L= 15 pF,
CMOS Signal Levels.
V_CM = 1000V, T_A = 25°C, I_F = 2.2 mA,
C_L= 15 pF, V_I = 5V, (R_T = 1.6 k) or
V_I = 3.3V, (R_T = 840 ),
CMOS Signal Levels, Figure 18
V_CM = 1000V, T_A = 25°C, I_F = 0 mA,
C_L= 15 pF, V_I = 0V, (R_T = 1.6 k) or
(R_T = 840), CMOS Signal Levels,
Figure 18
a. t_PHL propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% V_DD of the falling edge of the V_O signal. t_PLH
propagation delay is measured from the 50% (Vin or I_F) on the rising edge of the input pulse to the 50% level of the rising edge of the V_O signal.
b. PWD is defined as |t_PHL – t_PLH|.
c. t_PSK is equal to the magnitude of the worst case difference in t_PHL and/or t_PLH that will be seen between units at any given temperature within the
recommended operating conditions.
d. CM_H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
e. CM_L is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state.
NOTE Use of a 0.1 μF bypass capacitor connected between V_DD and ground is recommended.
Package Characteristics
All typical at T_A = 25°C.
Table 9 Package Characteristics
Parameter
Input-Output Insulation
Input-Output Resistance
Input-Output Capacitance
Symbol Part Number
Min. Typ.
V_ISO ACPL-M21L/024L/021L 3750
ACPL-W21L/K24L
5000
R_I-O
10¹²
C_I-O
0.6
Max. Units
Test Conditions
Vrms RH < 50% for 1 min., T_A = 25°C

V_I-O = 500 V
pF
f = 1 MHz, T_A = 25°C
Broadcom
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