DEMO-MGA-13X16 Datasheet, PDF (1/11 Pages) Broadcom Corporation. – High Gain, High Linearity, Very Low Noise Amplifier

MGA-13216
High Gain, High Linearity, Very Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-13216 is a two stage, easy-to-
use GaAs MMIC Low Noise Amplifier (LNA). The LNA has
low noise with good input return loss and high linearity
achieved through the use of Avago Technologies’ propri-
etary 0.25 Pm GaAs Enhancement-mode pHEMT process.
Minimum matching needed for input, output and the
inter-stage between the two LNA.
It is designed for optimum use between 1.5 GHz to 2.5
GHz. For optimum performance at lower frequency from
400 MHz to 1.5 GHz, the MGA-13116 is recommended.
Both MGA-13216 & MGA-13116 share the same package
and pinout configuration.
Pin Configuration and Package Marking
4.0 x 4.0 x 0.85 mm³ 16-lead QFN
AVAGO
13216
YYWW
XXXX
12
11
GND
10
9
Pin 2 Vbias
1 ^{Pin 3 RFinQ1}
Pin 10 RFoutQ2
2 Pin 11 RFoutQ2
3
Pin 13 RFinQ2
Pin 16 RFoutQ1
4
All other pins NC
– Not Connected
Features
x Optimum frequency of operation 1.5 GHz – 2.5 GHz
x Very low noise figure
x High gain
x High linearity performance
x Excellent isolation
x GaAs E-pHEMT Technology^[1]
x Low cost small package size: 4.0 x 4.0 x 0.85 mm³
Specifications
1.95 GHz; Q1: 5 V, 53 mA (typ) Q2: 5 V, 122 mA (typ)
x 0.61 dB Noise Figure
x 35.8 dB Gain
x 46 dB RFoutQ1 to RFinQ2 Isolation
x 40.5 dBm Output IP3
x 23.6 dBm Output Power at 1dB gain compression
Applications
x Low noise amplifier for cellular infrastructure including
GSM, CDMA, and W-CDMA.
x Other very low noise applications.
TOP VIEW
BOTTOM VIEW
Note:
Package marking provides orientation and identification
“13216” = Device Part Number
“YYWW” = Work Week and Year of Manufacture
“XXXX” = Lot Number
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V
ESD Human Body Model = 650 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Simplified Schematic
C9
R3
C8
Vdd1
C10
R4
R2
C7
L3
C6 R1
L1
RFIN _C1
16 15
1
2 _Q1bias
14 13
12
11
Q1
3
4
56
Q2
10
9
78
Vdd2
C5
C4
C3
L2
C2 ^RFOUT
Notes: Enhancement mode technology employs positive gate bias,
thereby eliminating the need of negative gate voltage associated with
conventional depletion mode devices.