BL7442LV Datasheet, PDF (3/10 Pages) SHANGHAI BELLING CO., LTD. – Low voltage Intelligent 2K bits EEPROM

BL7442LV Low voltage
Intelligent 2K bits EEPROM
Additionally to the above functions the BL7442LV provides a security code logic which
controls the write/erase access to the memory. For this purpose ,the BL7442LV contains a 4-byte
security memory with an error counter EC (bit 0 to bit 2) and 3 bytes reference data(figure
2).These 3 bytes as a whole are called programmable security code (PSC). After power on the
whole memory, except for the reference data, BL7442LV type B can only be read. Writing and
erasing is only possible after a successful comparison of verification data with the internal
reference data. After power on the whole memory,BL7442LV type A is neither written, erased nor
read. Reading, writing and erasing is only possible after a successful comparison of verification
data with the internal reference data. After three successive unsuccessful comparisons the error
counter blocks any subsequent attempt, and hence any possibility to write and erase.
Transmission Protocol
The transmission protocol is a two wire link protocol between the interface device IFD and
the integrated circuit IC. It is identical to the protocol type “S=10”. All data changes on I/O are
initiated by the falling edge on CLK.
The transmission protocol consists of the 4 modes:
(1)Reset and Answer-to-Reset
(2)Command Mode
(3)Outgoing Data Mode
(4)Processing Mode
(1) Reset and Answer-to-Reset (BL7442LV type B only)
Answer-to-Reset takes place according to ISO standard 7816-3.The reset can be given at any time
during operation. In the beginning, the address counter id set to zero together with a clock pulse and the first
data bit (LSB) is output to I/O when RST is set from state H to state L. Under a continuous input of additional
31 clock pulses the contents of the first 4 EEPROM addresses can be read out. The 33^rd clock pulse
switches I/O to state H (figure 3). During Answer-to-Reset any start and stop condition is ignored.
VCC
RST
1
2
3
4
...
CLK
1
2
3
...
I/O
31
32
30
31
32
RST
td4
td4
tH
CLK
tL
td2
td5
I/O
Figure 3 Reset and Answer-to-Reset
(2) Command Mode
After the Answer-to-Reset the chip waits for a command. Every command begins with a start condition,
includes a 3 bytes long command entry followed by an additional clock pulse and ends with a stop condition
(figure 4).
--Start condition: Falling edge on I/O during CLK in state H
--Stop condition: Rising edge on I/O during CLK in state H
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Total 10 Pages
8/16/2006