BL24C512G Datasheet, PDF (1/15 Pages) SHANGHAI BELLING CO., LTD. – Filtered inputs for noise suppression

Shanghai Belling Corp., Ltd
BL24C512G
 Features
 Two-Wire Serial Interface, I²C^TM Compatible
– Bi-directional data transfer protocol
 Wide-voltage Operation
– VCC = 1.7V to 5.5V
 Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
 Standby current (max.): 1 A, 1.7V
 Operating current (max.): 2 mA, 1.7V
 Hardware Data Protection
– Write Protect Pin
 Sequential & Random Read Features
 Memory organization: 65,536 x 8 bits
 Description
The BL24C512G are EEPROM devices that use the
industrial standard 2-wire interface for communications. The
BL24C512G contains a memory array of 512K-bits
(65,536x8), which is organized in 128-byte per page.
The EEPROM can operate in a wide voltage range from
1.7V to 5.5V which fits most application. This product can
provide a low-power 2-wire EEPROM solution. The device
is offered in Lead-free, RoHS, halogen free or Green. The
available package types are 8-pin SOIC/SOP, TSSOP, DFN
and CSP.
The BL24C512G is compatible with the industrial standard
2-wire bus protocol. If in case the bus is not responded, a
new sent Op-code command will reset the bus and the
device will respond correctly. The simple bus consists of the
Serial Clock wire (SCL) and the Serial Data wire (SDA).
Utilizing such bus protocol, a Master device, such as a
microcontroller, can usually control one or more Slave
devices, alike this BL24C512G. The bit stream over the
SDA line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address within
 Page Size: 128 bytes
 Page write mode
– Up to 128 bytes per page write
 Self timed write cycle with auto clear: 5ms (max.)
 Filtered inputs for noise suppression
 High-reliability
– Endurance: 1 million cycles
– Data retention: 100 years
 Industrial temperature grades
 Packages: SOIC/SOP, TSSOP, DFN and CSP
 Lead-free, RoHS, Halogen free, Green
that Slave device, and a series of data, if appropriate. The
BL24C512G also has a Write Protect pin (WP) to allow
blocking any write operations over specified memory area.
Under no circumstance, the device will be hung up. In order
to refrain the state machine entering into a wrong state
during power-up sequence or a power toggle off-on
condition, a power on reset circuit is embedded. During
power-up, the device does not respond to any instructions
until the supply voltage (VCC) has reached an acceptable
stable level above the reset threshold voltage. Once VCC
passes the power on reset threshold, the device is reset
and enters into the Standby mode. This would also avoid
any inadvertent Write operations during power-up stage.
During power-down process, the device will enter into
standby mode, once VCC drops below the power on reset
threshold voltage. In addition, the device will be in standby
mode after receiving the Stop command, provided that no
internal write operation is in progress. Nevertheless, it is
illegal to send a command unless the VCC is within its
operating level.
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