AZ70XX_07 Datasheet, PDF (9/13 Pages) BCD Semiconductor Manufacturing Limited – VOLTAGE DETECTOR

VOLTAGE DETECTOR
Operating Diagram (Continued)
Figure 12 is a typical timing waveform for AZ70XX.
In normal steady-state operation when V_CC>V_DET-,
the output will be in a logic high state and V_OUT is
dependent upon the voltage that the pull-up resistor
connected to.
Here is some explanations for AZ70XX's operation.
1. When the input voltage V_CC falls below V_DET-, the
output will pull down to logic low after a delay time of
tpHL. In general, at rated output current and V_CC,
V_OUT can be pulled down to a voltage as low as within
0.4V from GND. (See the Electrical Characteristics
section). The voltage level V_DET- means the detect
voltage.
2. The output, V_OUT, will stay valid until V_CC falls
below the minimum operating voltage, V_OPR (0.8V
Preliminary Datasheet
AZ70XX
typical). Below minimum operating voltage, the out-
put is undefined.
3. During power-up, V_OUT will remain undefined until
V_CC rises above V_OPR, at which time the output will
become valid. V_OUT will be in its active low state
while V_OPR<V_CC<V_DET+ (V_DET+=V_DET-+V_HYS).
V_DET+ is the release voltage. V_HYS means the hystere-
sis voltage and is the difference voltage between the
V_DET+ and V_DET-.
4. When V_CC rises above V_DET+, the output will be in
its inactive state. After a delay time of tpLH, V_OUT
will be in its logic high state .
Typical Applications
1
V_CC
AZ70XX
OUT ³
GND
LED
2
V_CC
R1
220
1
V_CC
AZ70XX
R1
3.3k
OUT ³
GND
2
+
C1
1 µF
V_CC +5V
V_CC
RESET ^CPU
GND
Figure 13. Low Voltage Indicator
Figure 14. CPU Resetting Circuit
Mar. 2007 Rev. 1. 5
BCD Semiconductor Manufacturing Limited
9