AZ70XX Datasheet, PDF (9/12 Pages) BCD Semiconductor Manufacturing Limited – VOLTAGE DETECTOR

Preliminary Datasheet
VOLTAGE DETECTOR
AZ70XX
Operating Diagram (Continued)

AZ70XX
Figure 12 is a typical timing waveform for AZ70XX
during power-up and temporary power-down period.
Here is some explanations for AZ70XX's operation.
1. During power-up period, V_OUT will remain
undefined until V_CC rises above V_OPR (typically
0.8V). After that moment, the output will become
valid and will be at its logic low state while
V_OPR<V_CC<V_S for power-up operating.
3. During power-down, after a delay time of tpHL
from the moment V_CC<V_S-V_HYS, V_OUT will be at its
logic low state. In general, at rated output current and
V_CC, V_OUT can be pulled down to a voltage as low as
within 0.4V from GND. (See the Electrical
Characteristics section).
4. V_OUT will be at its logic low state while V_S-
V_HYS>V_CC>V_OPR for power-down operating.
2. After a delay time of tpLH from the moment
V_CC>V_S, the V_OUT will be at its logic high state. In
general, V_OUT is dependent upon the voltage that the
pull up resistor connected to.
5. After V_CC falls below V_OPR, the output is
undefined.
Typical Applications
1
V_CC
AZ70XX
OUT ³
GND
LED
2
V_CC
R1
220
1
V_CC
AZ70XX
R1
3.3k
OUT ³
GND
2
+
C1
1 µF
V_CC +5V
V_CC
RESET ^CPU
GND
Figure 13. Low Voltage Indicator
Figure 14. CPU Resetting Circuit
Jul. 2005 Rev. 1. 3
BCD Semiconductor Manufacturing Limited
9