AZ809A_10 Datasheet, PDF (8/11 Pages) BCD Semiconductor Manufacturing Limited – 3-PIN MICROPROCESSOR RESET CIRCUIT

3-PIN MICROPROCESSOR RESET CIRCUIT
Operating Diagram
V_CC
V_TH
Data Sheet
AZ809A
V_CC (min)
RESET
Time
Output
Undefined
240ms
Typical
20 µ s
Typical
Reset Active
Timeout Period
240ms
Typical
Time
The AZ809A asserts a reset signal LOW whenever the VCC supply voltage is below the threshold
voltage and remains asserted for 240ms typically after the VCC has risen above the threshold.
Figure 11. Reset Timing Diagram of AZ809A
Application Information
Valid RESET with V_CC under 1.0 V
The AZ809A RESET output is valid to V_CC=1.0V.
Below this voltage, the output becomes an open circuit
and doesn't sink current. Therefore, high-impedance
CMOS logic input connected to RESET can drift to
undetermined voltages.
To ensure that the AZ809A RESET is in a known state
when V_CC is under 1.0V, a 100KΩ pull-down resistor
between the RESET pin and GND is recommended to
discharge stray capacitances and maintain the output
low.
VCC
AZ809A
RESET
GND
R1
100kΩ
Oct. 2010 Rev. 1. 3
Figure 12. RESET Valid to V_CC=0V
BCD Semiconductor Manufacturing Limited
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