AP3968 Datasheet, PDF (10/15 Pages) BCD Semiconductor Manufacturing Limited – Primary Side Power Switcher for Off-line SMPS Low Total Cost Solution

Preliminary Datasheet
Primary Side Power Switcher for Off-line SMPS
AP3968/69/70/70S
voltage. Assuming the secondary winding is master,
the auxiliary winding is slave during the D1 on-time.
The auxiliary voltage is given by:
( ) V_AUX
=
N _AUX
N_S
⋅
Vo + V_d
…………(5)
Where V_d is the diode forward drop voltage, N_AUX is
the turns of auxiliary winding, and N_S is the turns of
secondary winding.
discharging or charging the built-in capacitance
connected. This fixed proportion is
Tons ₌ 4 _{………… (6)}
Toffs 3
The relation between the output constant-current and
secondary peak current Ipks is given by:
Iout = ¹ ⋅ Ipks⋅ ^{Tons …………(7)}
2
Tons + Toffs
At the instant of D1 turn-on, the primary current
transfers to the secondary at an amplitude of:
Ipks = ^NP ⋅ Ipk ^{…………(8)}
N_S
Thus the output constant current is given by:
Figure 9. Auxiliary Voltage Waveform
The output voltage is different from the secondary
voltage in a diode forward drop voltage V_d which
depends on the current. If the secondary voltage is
always detected at a constant secondary current, the
difference between the output voltage and the
secondary voltage will be a fixed V_d. The voltage
detection point is portion of Tons after D1 is turned
on. The CV loop control function of
AP3968/69/70/70S then generates a D1 off-time to
regulate the output voltage.
Constant Current Operation
The AP3968/69/70/70S is designed to work in
constant current (CC) mode. Figure 10 shows the
secondary current waveforms.
Iout = ² ⋅ ^NP ⋅ Ipk ^{…………(9)}
7 N_S
Leading Edge Blanking (LEB)
When the power switch is turned on, a turn-on spike
on the output pulse rising edge will occur on the
sense-resistor. To avoid false termination of the
switching pulse, a typical 500ns leading edge
blanking is built in. During this blanking period, the
current sense comparator is disabled and the gate
driver can not be switched off.
The built-in LEB in AP3968/69/70/70S has shorter
delay time from current sense terminal to output
pulse than those IC solutions adopting external RC
filter as LEB.
Built-in Cable Compensation
The AP3968/69/70/70S has built-in fixed voltage of
0.35V typical to compensate the drop of output cable
when the load is changed from zero to full load. A
typical 0.01µF external capacitor connected to the
CPC pin is used to smooth voltage signal for cable
compensation.
Figure 10. Secondary Current Waveform
In CC operation, the CC loop control function of
AP3968/69/70/70S will keep a fixed proportion
between D1 on-time Tons and D1 off-time Toffs by
Over Temperature Protection
The AP3968/69/70/70S has internal thermal sensing
circuit to shut down the PFM driver output when the
die temperature reaches 160ºC typical. When the die
temperature drops about 40ºC, the IC will recover
automatically to normal operation.
Dec. 2011 Rev. 1. 4
BCD Semiconductor Manufacturing Limited
10