AP2302 Datasheet, PDF (1/13 Pages) BCD Semiconductor Manufacturing Limited – 3A DDR TERMINATION REGULATOR

Preliminary Datasheet
3A DDR TERMINATION REGULATOR
General Description
Features
AP2302
The AP2302 linear regulator is designed to meet the
JEDEC specification SSTL-2 and SSTL-18 for termi-
nation of DDR-SDRAM. The regulator can sink or
source up to 3A current continuously, offers enough
current for most DDR applications. Output voltage is
designed to track the reference voltage within a 2%
(DDR I) and 3% (DDR II) tolerance for load regulation
while preventing shooting through on the output stage.
On-chip thermal limiting provides protection against a
combination of high current and ambient temperature
which would create an excessive junction temperature.
· Support Both DDR I (1.25V_TT) and DDR II
(0.9V_TT) Requirements
· Source and Sink Current up to 3A
· High Accuracy Output Voltage at Full-load
· Adjustable V_OUT by External Resistors
· Shutdown for Standby or Suspend Mode
Operation with High-impedance Output
Applications
The AP2302, used in conjunction with series termina-
tion resistors, provides an excellent voltage source for
·
DDR-SDRAM Termination
active termination schemes of high speed transmission ^{· DDR-II Termination}
lines as those seen in high speed memory buses and ^{· SSTL-2 Termination}
distributed backplane designs.
The AP2302 is available in SOIC-8, TO-252-5L and
TO-263-5L packages.
SOIC-8
TO-252-5L
TO-263-5L
Jul. 2006 Rev. 1. 2
Figure 1. Package Types of AP2302
BCD Semiconductor Manufacturing Limited
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