AZ100LVEL16VT_12 Datasheet, PDF (3/9 Pages) Arizona Microtek, Inc – PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable

Arizona Microtek, Inc.
ENGINEERING NOTES
AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
The AZ100LVEL16VT is a specialized oscillator gain stage with a high gain output buffer including an enable. The
Q_HG/Q¯ _HG outputs have a voltage gain several times greater than the Q¯ output. When the E¯N¯ input is LOW, the Q¯ and
Q_HG/Q¯ _HG outputs follow the data inputs. When E¯N¯ is HIGH, the Q_HG output is forced high and the Q¯ _HG output is forced
low.
For the AZ100LVEL16VTNA, both D and D¯ inputs are brought out and tied to the V_BB pin through 470Ω internal bias
resistors. In the AZ100LVEL16VTNB, the D¯ input is internally tied directly to the V_BB pin and the D input is tied to the
V_BB pin through a 470Ω internal bias resistor. Bypassing V_BB to ground with a 0.01 µF capacitor is recommended.
D
EN
Q
Q
Q_HG
Q_HG
Figure 3 -Timing Diagram
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May 2012, Rev 2.0