AZ10LVEL33 Datasheet, PDF (1/10 Pages) Arizona Microtek, Inc – ECL/PECL ÷4 Divider

ARIZONA MICROTEK, INC.
AZ10LVEL33
AZ100LVEL33
ECL/PECL ÷4 Divider
FEATURES
PACKAGE AVAILABILITY
• Green / RoHS Compliant /
Lead (Pb) Free package available
• Operating Range of 3.0V to 5.5V
PACKAGE
MLP 8 (2x2) Green
/ RoHS Compliant /
Lead (Pb) Free
PART NUMBER
AZ100LVEL33NG
MARKING
C3G
<Date Code>
NOTES
1,2
• 470ps Propagation Delay
• 4.0GHz Toggle Frequency
MLP 16 (3x3)
• Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor ^{SOIC 8}
MC10EL33, MC100EL33,
and MC100LVEL33
SOIC 8
• Transistor Count = 91 Devices
• IBIS Model Files Available on Arizona
TSSOP 8
AZ10/100LVEL33L
AZ10LVEL33D
AZ100LVEL33D
AZ10LVEL33T
AZM
L33
<Date Code>
AZM10
LVEL33
AZM100
LVEL33
AZT
LV33
1,2
1,2,3
1,2,3
1,2,3
Microtek Web Site
TSSOP 8
AZ100LVEL33T
AZH
LV33
1,2,3
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K
parts) Tape & Reel.
2 Date code format: “Y” or “YY” for year followed by “WW” for week.
3 Date code “YWW” or “YYWW” on underside of part.
DESCRIPTION
The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q
Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET
allows for the synchronization of multiple LVEL33’s in a system.
The LVEL33 provides a V_BB output for single-end use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the V_BB reference should be connected to one side of the CLK/ C¯¯L¯K¯ differential
input pair. The input signal is then fed to the other CLK/ C¯¯L¯K¯ input. The V_BB pin can support 1.0mA sink/source
current. When used, the V_BB pin should be bypassed to ground via a 0.01μF capacitor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PIN DESCRIPTION
PIN
CLK, C¯L¯¯K
RESET
V_BB
Q, Q¯
V_CC
V_EE
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
RESET
CLK
CLK
V_BB
LOGIC DIAGRAM
R
Q
÷4
Q
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com