AZ10LVEL11 Datasheet, PDF (1/7 Pages) Arizona Microtek, Inc – ECL/PECL 1:2 Differential Fanout Buffer

ARIZONA MICROTEK, INC.
AZ10LVEL11
AZ100LVEL11
ECL/PECL 1:2 Differential Fanout Buffer
FEATURES
PACKAGE AVAILABILITY
• 265ps Propagation Delay
• 5ps Skew Between Outputs
• High Bandwidth Output Transitions
• Internal Input Pulldown Resistors
• Operating Range of 3.0V to 5.5V
• Direct Replacement for ON Semi
MC100LVEL11, MC10EL11
& MC100EL11
• Transistor Count = 51
DESCRIPTION
PACKAGE
PART NUMBER MARKING NOTES
SOIC 8
AZ10LVEL11D
AZM10
LVEL11
1,2
SOIC 8
AZ100LVEL11D
AZM100
LVEL11
1,2
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ10LVEL11D+
AZM10+
LVEL11
1,2
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ100LVEL11D+
AZM100+
LVEL11
1,2
TSSOP 8
AZ10LVEL11T
AZT
LV11
1,2
TSSOP 8
AZ100LVEL11T
AZH
LV11
1,2
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
AZ100LVEL11T+
AZH+
LV11
1,2
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2 Date code “YWW” or “YYWW” on underside of part.
The AZ10/100LVEL11 is a differential 1:2 fanout gate. The device is functionally similar to the E111 device
but with higher performance capabilities. Having within-device skews and output transition times significantly
improved over the E111, the AZ10/100LVEL11 is ideally suited for those applications that require the ultimate in
AC performance.
The differential inputs of the AZ10/100LVEL11 employ clamping circuitry to maintain stability under open
input conditions. If the inputs are left open, the Q outputs will go LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
D, D¯
Q0, Q¯¯0, Q1, Q¯¯1
V_CC
V_EE
FUNCTION
Data Inputs
Data Outputs
Positive Supply
Negative Supply
Q0 1
Q0 2
Q1 3
8 ^VCC
7D
6D
Q1 4
5 VEE
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com