AZ10LVE111 Datasheet, PDF (1/6 Pages) Arizona Microtek, Inc – ECL/PECL 1:9 Differential Clock Driver

ARIZONA MICROTEK, INC.
AZ10LVE111
AZ100LVE111
ECL/PECL 1:9 Differential Clock Driver
FEATURES
• Operating Range of 3.0V to 5.5V
• Low Skew
• Guaranteed Skew Spec
• Differential Design
• V_BB Output
• 75kΩ Internal Pulldown Resistors
• Direct Replacement for ON
Semiconductor MC100LVE111
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
PART NO.
MARKING NOTES
PLCC 28
AZ10LVE111FN
AZ10
LVE111
1,2
<Date Code>
PLCC 28
AZ100LVE111FN
AZ100
LVE111
1,2
<Date Code>
PLCC 28 RoHS
Compliant / Lead
(Pb) Free
AZ100+
AZ100LVE111FN+ LVE111
1,2
<Date Code>
1 Add R2 at end of part number for 13 inch (750 parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The
IN signal is fanned-out to nine identical differential outputs.
The AZ100LVE111 provides a V_BB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the V_BB reference should be connected to one side of the IN/I¯N¯
differential input pair. The input signal is then fed to the other IN/I¯N¯ input. When used, the V_BB pin should be
bypassed to ground via a 0.01μF capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent t_pd distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same V_CCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com