AZ10ELT20 Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – CMOS/TTL to Differential PECL Translator

ARIZONA MICROTEK, INC.
AZ10ELT20
AZ100ELT20
CMOS/TTL to Differential PECL Translator
FEATURES
PACKAGE AVAILABILITY
• 0.5ns Typical Propagation Delay
• Differential PECL Outputs
PACKAGE
MLP 8 (2x2x0.75)
PART NUMBER
AZ100ELT20N
MARKING NOTES
TC
<Date Code>
1,2
• Flow Through Pinouts
• Operating Range of +3.0V to +5.5V
• Direct Replacement for ON Semi
MC100ELT20 & Micrel SY89329V
• Available in 2x2 and 3x3 mm MLP
Packages
• IBIS Model Files Available on
Arizona Microtek Website
MLP 8 (2x2x0.75)
Green / RoHS
Compliant / Lead
(Pb) Free
MLP 16 (3x3)
MLP 16 (3x3)
Green / RoHS
Compliant / Lead
(Pb) Free
AZ100ELT20NG
AZ10/100ELT20L
AZ10/100ELT20LG
TCG
<Date Code>
1,2
AZM
T20
1,2
<Date Code>
AZMG
T20
1,2
<Date Code>
SOIC 8
AZ10ELT20D
AZM10
ELT20
1,2,3
SOIC 8
AZ100ELT20D
AZM100
ELT20
1,2,3
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ100ELT20D+
AZM100+
ELT20
1,2,3
DESCRIPTION
SOIC 8 Green /
RoHS Compliant /
Lead (Pb) Free
AZ100ELT20DG
AZM100G
ELT20
1,2,3
The AZ10/100ELT20 is a
CMOS/TTL to differential PECL
TSSOP 8
AZ100ELT20T
AZH
LT20
1,2,3
translator. It operates with a single power
supply of +3.0 to +5.5 volts, making it
ideal for both LVCMOS/LVTTL and
CMOS/TTL applications. The extremely
small MLP 8 2x2 mm package makes it
ideal for those applications where space,
performance and low power are at a
premium.
TSSOP 8 Green /
RoHS Compliant /
Lead (Pb) Free
AZ100ELT20TG
AZHG
LT20
1,2,3
DIE
AZ10/100ELT20XP N/A
4
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K
parts) Tape & Reel.
2 Date code format: “Y” or “YY” for year followed by “WW” for week.
3 Date code “YWW” or “YYWW” on underside of part.
4 Waffle Pack.
When the D input is left floating, the Q output is forced HIGH, and the Q¯ output is forced LOW.
The ELT20 is available in both PECL standards: the AZ10ELT20 is compatible with PECL 10K logic levels
while the AZ100ELT20 is compatible with PECL 100K logic levels.
NOTE: Specifications in the PECL tables are valid when thermal equilibrium is established.
BLOCK DIAGRAM
Q
D
Q
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com