AZ10EL32 Datasheet, PDF (1/6 Pages) List of Unclassifed Manufacturers – ECL/PECL ÷ 2 Divider

ARIZONA MICROTEK, INC.
AZ10EL32
AZ100EL32
ECL/PECL ÷ 2 Divider
FEATURES
• 510ps Propagation Delay
• 3.0GHz Toggle Frequency
• High Bandwidth Output Transitions
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON
Semiconductor MC10EL32 &
MC100EL32
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
PART NUMBER MARKING NOTES
SOIC 8
AZ10EL32D
AZM10
EL32
1,2
SOIC 8
AZ100EL32D
AZM100
EL32
1,2
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ100EL32D+
AZM100+
EL32
1,2
TSSOP 8
AZ10EL32T
AZT
EL32
1,2
TSSOP 8
AZ100LVEL32T
AZH
EL32
1,2
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2 Date code format: “Y” or “YY” for year followed by “WW” for week on
underside of part.
The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of
multiple EL32’s in a system.
The EL32 provides a V_BB output for single-ended use or a DC bias reference for AC coupling to the device. For
single-ended input applications, the V_BB reference should be connected to one side of the CLK/¯C¯L¯K¯ differential input
pair. The input signal is then fed to the other CLK/¯C¯L¯K¯ input. The V_BB pin should be used only as a bias for the
EL32 as its sink/source capability is limited. When used, the V_BB pin should be bypassed to ground via a 0.01μF
capacitor.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
CLK, C¯L¯¯K
RESET
V_BB
Q, Q¯
V_CC
V_EE
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
RESET 1
CLK 2
CLK 3
V_BB 4
8 VCC
R
7Q
÷2
6Q
5 VEE
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com