AZ10E142 Datasheet, PDF (1/5 Pages) Arizona Microtek, Inc – ECL/PECL 9-bit Shift Register

ARIZONA MICROTEK, INC.
AZ10E142
AZ100E142
ECL/PECL 9-bit Shift Register
FEATURES
PACKAGE AVAILABILITY
• 700 MHz Minimum Shift Frequency
PACKAGE PART NUMBER MARKING NOTES
• 9-Bit for Byte-Parity Application
• Asynchronous Master Reset
PLCC 28
AZ10E142FN
AZM10E142
<Date Code>
1,2
• Dual Clocks
• Operating Range of 4.2V to 5.46V
PLCC 28
AZ100E142FN
AZM100E142
<Date Code>
1,2
•
75kΩ Internal Input Pulldown Resistors
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
• Direct Replacement for ON Semi
MC10E142 & MC100E142
DESCRIPTION
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs
serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data,
while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift
direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of
CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
SEL
D8
D7
D6
D5
V_CCO
Q8
25
24
23
22
21
20
19
MR
26
18
Q7
CLK1
27
17
Q6
CLK2
28
V_EE
1
S-IN
2
Pinout: 28-lead
PLCC (top view)
16
V_CC
15
Q5
14
V_CCO
D0
3
13
Q4
D1
4
12
Q3
5
6
7
8
9
10
11
D2
D3
D4 V_CCO
Q0
Q1
Q2
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com