AZ10E131 Datasheet, PDF (1/6 Pages) Arizona Microtek, Inc – ECL/PECL 4-bit D Flip-Flop

ARIZONA MICROTEK, INC.
AZ10E131
AZ100E131
ECL/PECL 4-bit D Flip-Flop
FEATURES
PACKAGE AVAILABILITY
• 1100 MHz Min. Toggle Frequency
• Differential Outputs
PACKAGE PART NUMBER MARKING NOTES
• Individual and Common Clocks
• Individual Resets (asynchronous)
• Paired Sets (asynchronous)
• Operating Range of 4.2V to 5.46V
PLCC 28
AZ10E131FN
AZM10E131
<Date Code>
1,2
PLCC 28
AZ100E131FN
AZM100E131
<Date Code>
1,2
1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
• 75kΩ Internal Input Pulldown Resistors 2 Date code format: “YY” for year followed by “WW” for week.
• Direct Replacement for On Semiconductor
MC10E131 & MC100E131
DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be
clocked separately by holding Common Clock (C_C) LOW and using the Clock Enable (C¯¯En) inputs for clocking.
Common clocking is achieved by holding the C¯¯En inputs LOW and using C_C to clock all four flip-flops. In this
case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs,
with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both C_C and C¯¯En are LOW, and transfers to the slave when either C_C or C¯¯En (or
both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
R3
D2
CE2
R2
V_CCO
Q3
Q3
25
24
23
22
21
20
19
CE3
26
18
Q2
D3
27
17
Q2
S12
28
V_EE
1
C_C
2
S03
3
Pinout: 28-Lead
PLCC (top view)
16
V_CC
15
Q1
14
Q1
13
Q0
D0
4
12
Q0
5
6
7
8
9
10
11
CE0
R0
D1 CE1
R1
NC
V_CCO
* All V_CC and V_CCO pins are tied together on the die.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com