AZ10E116 Datasheet, PDF (1/5 Pages) Arizona Microtek, Inc – ECL/PECL Quint Differential Line Receiver

ARIZONA MICROTEK, INC.
AZ10E116
AZ100E116
ECL/PECL Quint Differential Line Receiver
FEATURES
PACKAGE AVAILABILITY
• 500ps Maximum Propagation Delay
PACKAGE PART NUMBER MARKING NOTES
• Dedicated V_CCO Pin for Each Receiver
• Operating Range of 4.2V to 5.46V
PLCC 28
AZ10E116FN
AZM10E116
<Date Code>
1,2
• 75kΩ Internal Input Pulldown Resistors
PLCC 28
• Direct Replacement for ON Semiconductor
AZ100E116FN
AZM100E116
<Date Code>
1,2
MC10E116 & MC100E116
1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
DESCRIPTION
The AZ10/100E116 is a quint differential line receiver with emitter-follower outputs. The E116 provides a V_BB
output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input
applications, the V_BB reference should be connected to one side of the Dn/D¯ n differential input pair. The input
signal is then fed to the other Dn/D¯ n input. The V_BB pin should be used only as a bias for the E116 as its sink/source
capability is limited. When used, the V_BB pin should be bypassed to ground via a 0.01μF capacitor.
The receiver design features clamp circuitry to cause a defined state if both the inverting and non-inverting
inputs are left open; in this case the Q output goes LOW, while the Q¯ output goes HIGH. This feature makes the
device ideal for twisted pair applications.
If both inverting and non-inverting inputs are at an equal potential of > V_CC -2.5V, the receiver does not go
to a defined state. This condition may produce output voltage levels between HIGH and LOW.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com