AZ100LVEL16VR Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable

ARIZONA MICROTEK, INC.
AZ100LVEL16VR
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
• Green and RoHS Compliant /
Lead (Pb) Free Packages Available
• Enhanced Enable Operation
• High Bandwidth for ≥1GHz
• Similar Operation as AZ100EL16VO
• Minimizes External Components
• Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
• Available in a MLP 16 or MLP 8
Package
• S–Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
PACKAGE AVAILABILITY
PACKAGE
PART NO.
MARKING NOTES
AZM
MLP 16 (3x3)
AZ100LVEL16VRL
16R
1,2
<Date Code>
MLP 16 (3x3) RoHS
AZM+
Compliant / Lead
AZ100LVEL16VRL+ 16R
1,2
(Pb) Free
<Date Code>
MLP 8 (2x2) Green /
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VRNEG
R5G
<Date Code>
1,2
DIE
AZ100LVEL16VRX
N/A
3
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2 Date code format: “Y” for year followed by “WW” for week.
3 Waffle Pack
DESCRIPTION
The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable
function. The Q_HG/Q¯ _HG outputs have voltage gain several times greater than the Q/Q¯ outputs.
MLP 16, 3x3 mm Package (VRL) or DIE (VRX)
The AZ100LVEL16VR provides a selectable Q_HG/Q¯ _HG enable that allows continuous oscillator operation via
the Q/Q¯ outputs. The enable truth table on the next page shows the operating modes. Leaving EN-SEL open (NC)
selects PECL/ECL operation for the EN pad/pin. In this mode the Q_HG/Q¯ _HG outputs are enabled when EN is left
open (NC) or set to a PECL/ECL low.
Connecting EN-SEL to V_CC, V_EE or V_BB selects CMOS operation for the EN pad/pin. When EN-SEL is tied to
V_EE, the Q_HG/Q¯ _HG outputs are disabled when EN is left open (NC). When EN-SEL is tied to V_CC or V_BB, the Q_HG/Q¯
HG ^{outputs are enabled when EN is left open.1 This default logic condition can be overridden by a ≤20kΩ resistor}
connected to the opposite supply.
The AZ100LVEL16VR also provides a V_BB and 470Ω internal bias resistors from D to V_BB and D¯ to V_BB. The
V_BB pin supports 1.5mA sink/source current. V_BB should be bypassed to ground or V_CC with a 0.01 μF capacitor.
Outputs Q/Q¯ each have a selectable on-chip pull-down current source. See the current source truth table on the
next page for the supported values. External resistors may also be used to increase pull-down current to a maximum
total of 25mA for the Q/Q¯ outputs.
Each of the Q_HG/Q¯ _HG outputs has an optional on-chip pull-down current source of 10 mA. When pad/pin V_EEP is
left open (NC), the output current sources are disabled and the Q_HG /Q¯ _HG operate as standard PECL/ECL. When V_EEP
is connected to V_EE, the current sources are activated. The Q_HG /Q¯ _HG pull-down current can be decreased by using a
resistor between V_EEP and V_EE.
1_{This operational mode (EN-SEL to VCC or VBB) is not supported for date codes prior to 0428 (July 2004). EN-SEL to VEE is supported for all}
date codes.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com